Martín Vázquez

Orcid: 0000-0002-2574-8766

Affiliations:
  • National University of Central Buenos Aires (UNICEN), LabSET-INTIA, Tandil, Argentina
  • FASTA University, Faculty of Engineering, Buenos Aires, Argentina


According to our database1, Martín Vázquez authored at least 14 papers between 2009 and 2026.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of five.

Timeline

Legend:

Book  In proceedings  Article  PhD thesis  Dataset  Other 

Links

On csauthors.net:

Bibliography

2026
Optimal Design of IEEE-754 Decimal Floating-Point Multipliers in FPGAs for DPD and BID Encoding.
Circuits Syst. Signal Process., April, 2026

2024
Automated Parasite Control System Prototype Through Capsule Dosage Based on Image Processing.
IEEE Embed. Syst. Lett., September, 2024

Analysis and efficient implementation of IEEE-754 decimal floating point adders/subtractors in FPGAs for DPD and BID encoding.
J. Supercomput., May, 2024

Automatic Fecal Eggs Counting in Ruminants Using Xilinx DPU.
IEEE Embed. Syst. Lett., March, 2024

2023
FPGA-Based Accelerator for AI-Toolbox Reinforcement Learning Library.
IEEE Embed. Syst. Lett., June, 2023

2022
FPGA acceleration analysis of LibSVM predictors based on high-level synthesis.
J. Supercomput., 2022

2021
Radix-10 Restoring Square Root for 6-input LUTs Programmable Devices.
Circuits Syst. Signal Process., 2021

2019
Radix-10 decimal logarithm by direct selection for 6-input LUTs programmable devices.
Microprocess. Microsystems, 2019

2016
Real-time speckle image processing.
J. Real Time Image Process., 2016

2012
Correction to "Introducing Programmable Logic to Undergraduate Engineering Students in a Digital Electronics Course".
IEEE Trans. Educ., 2012

Introducing Programmable Logic to Undergraduate Engineering Students in a Digital Electronics Course.
IEEE Trans. Educ., 2012

2010
High-Speed FPGA 10's Complement Adders-Subtractors.
Int. J. Reconfigurable Comput., 2010

2009
Decimal Adders/Subtractors in FPGA: Efficient 6-input LUT Implementations.
Proceedings of the ReConFig'09: 2009 International Conference on Reconfigurable Computing and FPGAs, 2009

FPGA Implementations of BCD Multipliers.
Proceedings of the ReConFig'09: 2009 International Conference on Reconfigurable Computing and FPGAs, 2009


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