Marwan A. Jabri

According to our database1, Marwan A. Jabri authored at least 46 papers between 1987 and 2011.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

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Bibliography

2011
Representation, methods, and circuits for time-based conversion and computation.
Int. J. Circuit Theory Appl., 2011

2006
A Biologically Inspired Shape Representation Model Based on Part Decomposition.
Proceedings of the International Joint Conference on Neural Networks, 2006

2004
The 3G-324M Protocol for Conversational Video Telephony.
IEEE Multim., 2004

2002
Hierarchical Feature Extraction for Image Recognition.
J. VLSI Signal Process., 2002

Neural network models for the gaze shift system in the superior colliculus and cerebellum.
Neural Networks, 2002

2001
Multiresolution forecasting for futures trading using wavelet decompositions.
IEEE Trans. Neural Networks, 2001

Experimental Evaluation of Automatic Array Alignment in Parallelized Matlab.
J. Parallel Distributed Comput., 2001

Parallel Fiber Coding in the Cerebellum for Life-Long Learning.
Auton. Robots, 2001

2000
Properties of Independent Components of Self-Motion Optical Flow.
Proceedings of the 30th IEEE International Symposium on Multiple-Valued Logic, 2000

1999
Handwritten digit recognition by adaptive-subspace self-organizing map (ASSOM).
IEEE Trans. Neural Networks, 1999

A low-complexity intracardiac electrogram compression algorithm.
IEEE Trans. Biomed. Eng., 1999

Automatic Array Alignment in Parallel Matlab Scripts.
Proceedings of the 13th International Parallel Processing Symposium / 10th Symposium on Parallel and Distributed Processing (IPPS / SPDP '99), 1999

1998
Machine learning-based VLSI cells shape function estimation.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1998

Low resolution, degraded document recognition using neural networks and hidden Markov models.
Pattern Recognit. Lett., 1998

A Micropower CMOS Adaptive Amplitude and Shift Invariant Vector Quantiser.
Proceedings of the Advances in Neural Information Processing Systems 11, [NIPS Conference, Denver, Colorado, USA, November 30, 1998

A three-port adiabatic register file suitable for embedded applications.
Proceedings of the 1998 International Symposium on Low Power Electronics and Design, 1998

1997
Comparison of Human and Machine Word Recognition.
Proceedings of the Advances in Neural Information Processing Systems 10, 1997

1996
Classifier Architectures for Single Chamber Arrhythmia Recognition.
Appl. Intell., 1996

1995
A hybrid analog and digital VLSI neural network for intracardiac morphology classification.
IEEE J. Solid State Circuits, May, 1995

A low-power VLSI arrhythmia classifier.
IEEE Trans. Neural Networks, 1995

A silicon basis for synaptic plasticity.
Neural Process. Lett., 1995

A low-power network for on-line diagnosis of heart patients.
IEEE Micro, 1995

A Novel Channel Selection System in Cochlear Implants Using Artificial Neural Network.
Proceedings of the Advances in Neural Information Processing Systems 8, 1995

Neural Network Based Estimation of VLSI Building Block Dimensions from Schematic.
Proceedings of the 1995 IEEE International Symposium on Circuits and Systems, ISCAS 1995, Seattle, Washington, USA, April 30, 1995

1994
Building Rectangular Floorplans-A Graph Theoretical Approach.
VLSI Design, 1994

Learning with Product Units.
Proceedings of the Advances in Neural Information Processing Systems 7, 1994

ICEG Morphology Classification using an Analogue VLSI Neural Network.
Proceedings of the Advances in Neural Information Processing Systems 7, 1994

1993
Algorithmic and implementation issues in analog low power learning neural network chips.
J. VLSI Signal Process., 1993

Kakadu - A Low Power Analogue Neural Network Classifier.
Int. J. Neural Syst., 1993

Constructive Learning Using Internal Representation Conflicts.
Proceedings of the Advances in Neural Information Processing Systems 6, 1993

WATTLE: A Trainable Gain Analogue VLSI Neural Network.
Proceedings of the Advances in Neural Information Processing Systems 6, 1993

Extraction of high level sequential structure using recurrent neural networks and radial basis functions.
Proceedings of the First New Zealand International Two-Stream Conference on Artificial Neural Networks and Expert Systems, 1993

An analogue neural network using MCM technology.
Proceedings of the First New Zealand International Two-Stream Conference on Artificial Neural Networks and Expert Systems, 1993

1992
Analysis of the effects of quantization in multilayer neural networks using a statistical model.
IEEE Trans. Neural Networks, 1992

Summed Weight Neuron Perturbation: An O(N) Improvement Over Weight Perturbation.
Proceedings of the Advances in Neural Information Processing Systems 5, [NIPS Conference, Denver, Colorado, USA, November 30, 1992

A zero-skew clock routing scheme for VLSI circuits.
Proceedings of the 1992 IEEE/ACM International Conference on Computer-Aided Design, 1992

1991
Weight Perturbation: An Optimal Architecture and Learning Technique for Analog VLSI Feedforward and Recurrent Multilayer Networks.
Neural Comput., 1991

ANN Board Classification for Heart Defibrillators.
Proceedings of the Advances in Neural Information Processing Systems 4, 1991

1990
BREL - a Prolog Knowledge-based System Shell for VLSI CAD.
Proceedings of the 27th ACM/IEEE Design Automation Conference. Orlando, 1990

1989
Knowledge-based system design using prolog: the PIAF experience.
Knowl. Based Syst., 1989

PIAF: efficient IC floor planning.
IEEE Expert, 1989

Review of Design Automation: Automated Full-Custom VLSI Layout Using the Ulysses Design Environment.
AI Mag., 1989

Design and implementation of a formant speech synthesiser ASIC.
Proceedings of the IEEE International Conference on Acoustics, 1989

PIAF: A Knowledge-based/Algorithm Top-Down Floorplanning System.
Proceedings of the 26th ACM/IEEE Design Automation Conference, 1989

1988
Automatic Building of Graphs for Rectangular Dualisation.
Proceedings of the 25th ACM/IEEE Conference on Design Automation, 1988

1987
Implementation of a knowledge base for interpreting and driving integrated circuit floorplanning algorithms.
Artif. Intell. Eng., 1987


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