Masahiko Toyonaga

According to our database, Masahiko Toyonaga authored at least 14 papers between 1994 and 2020.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2020

A Tiny Neural Network Model for Estimating Next 24 Hour Temperature Transition.

Huidong Tang, Yuichiro Mori, Masahiko Toyonga

Proceedings of the International Conference on System Science and Engineering, 2020

2018

Facial Expression Sequence Recognition for a Japanese Sign Language Training System.

Keisuke Yabunaka, Yuichiro Mori, Masahiko Toyonaga

Proceedings of the 2018 Joint 10th International Conference on Soft Computing and Intelligent Systems (SCIS) and 19th International Symposium on Advanced Intelligent Systems (ISIS), 2018

Data-Glove for Japanese Sign Language Training System with Gyro-Sensor.

Yuichiro Mori, Masahiko Toyonaga

Proceedings of the 2018 Joint 10th International Conference on Soft Computing and Intelligent Systems (SCIS) and 19th International Symposium on Advanced Intelligent Systems (ISIS), 2018

A Single Filter CNN Performance for Basic Shape Classification.

Kenya Murata, Masataka Mito, Daisuke Eguchi, Yuichiro Mori, Masahiko Toyonaga

Proceedings of the 9th International Conference on Awareness Science and Technology, 2018

A Data Reconstruction Method for The Big-Data Analysis.

Masataka Mito, Kenya Murata, Daisuke Eguchi, Yuichiro Mori, Masahiko Toyonaga

Proceedings of the 9th International Conference on Awareness Science and Technology, 2018

2014

A critical net reshape-router for high-performance VLSI layout design.

Yusuke Morimoto, Mitsuru Matsushita, Michiaki Muraoka, Masahiko Toyonaga

Proceedings of the 2014 IEEE Asia Pacific Conference on Circuits and Systems, 2014

2013

A multilayer crosstalk avoidance router using restricted maze grids.

Yoshiya Fujii, Michiaki Muraoka, Masahiko Toyonaga

Proceedings of the IEEE 56th International Midwest Symposium on Circuits and Systems, 2013

A multilevel fingerprinting method for FPGA IP protection.

Tingyuan Nie, Yansheng Li, Lijian Zhou, Masahiko Toyonaga

Proceedings of the 2013 IEEE International Symposium on Circuits and Systems (ISCAS2013), 2013

2007

An Efficient and Reliable Watermarking System for IP Protection.

Tingyuan Nie, Masahiko Toyonaga

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2007

2005

A post layout watermarking method for IP protection.

Tingyuan Nie, Tomoo Kisaka, Masahiko Toyonaga

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005

A watermarking system for IP protection by a post layout incremental router.

Tingyuan Nie, Tomoo Kisaka, Masahiko Toyonaga

Proceedings of the 42nd Design Automation Conference, 2005

2002

A High-Speed and Low-Power Clock Tree Synthesis by Dynamic Clock Scheduling.

Keiichi Kurokawa, Takuya Yasui, Yoichi Matsumura, Masahiko Toyonaga, Atsushi Takahashi

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2002

2000

A practical clock tree synthesis for semi-synchronous circuits.

Masahiko Toyonaga, Keiichi Kurokawa, Takuya Yasui, Atsushi Takahashi

Proceedings of the 2000 International Symposium on Physical Design, 2000

1994

A New Approach of Fractional-Dimension Based Module Clustering for VLSI Layout.

Masahiko Toyonaga, Shih-Tsung Yang, Toshiro Akino, Isao Shirakawa

Proceedings of the 1994 IEEE International Symposium on Circuits and Systems, ISCAS 1994, London, England, UK, May 30, 1994