Isao Shirakawa

According to our database1, Isao Shirakawa authored at least 78 papers between 1977 and 2016.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Awards

IEEE Fellow

IEEE Fellow 1990, "For contributions to network theory and its applications to computer-aided circuit analysis and design.".

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Other 

Links

On csauthors.net:

Bibliography

2016
A real-time vital sensing system for persons during exercises.
Proceedings of the IEEE 6th International Conference on Consumer Electronics - Berlin, 2016

2014
Implementation of dynamic-range enhancement and super-resolution algorithms for medical image processing.
Proceedings of the IEEE International Conference on Consumer Electronics, 2014

Live demonstration: A battery smart sensor for smart grid.
Proceedings of the 2014 IEEE Asia Pacific Conference on Circuits and Systems, 2014

2013
Implementation of super-resolution scaler for Full HD and 4K video.
Proceedings of the IEEE Third International Conference on Consumer Electronics, 2013

2011
An automatic layout method for timing pulse generator of small LCD driver.
Proceedings of the 20th European Conference on Circuit Theory and Design, 2011

2008
Area-Efficient Reconfigurable Architecture for Media Processing.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2008

2007
Transistor Sizing of LCD Driver Circuit for Technology Migration.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2007

2006
A low-complexity FEC assignment scheme for motion JPEG2000 over wireless network.
IEEE Trans. Consumer Electron., 2006

A Sampling Switch Design Procedure for Active Matrix Liquid Crystal Displays.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2006

Real-Time Human Object Extraction Method for Mobile Systems Based on Color Space Segmentation.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2006

W-CDMA Channel Codec by Configurable Processors.
Intell. Autom. Soft Comput., 2006

2005
Embedded 3D sound movement system based on feature extraction of head-related transfer function.
IEEE Trans. Consumer Electron., 2005

Architecture of IEEE802.11i Cipher Algorithms for Embedded Systems.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2005

Design of Ogg Vorbis Decoder System for Embedded Platform.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2005

3D sound movement system for embedded applications.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005

Interconnect capacitance extraction for system LCD circuits.
Proceedings of the 15th ACM Great Lakes Symposium on VLSI 2005, 2005

A design scheme for sampling switch in active matrix LCD.
Proceedings of the 2005 European Conference on Circuit Theory and Design, 2005

2004
C-based hardware design of IMDCT accelerator for Ogg Vorbis decoder.
Proceedings of the 2004 12th European Signal Processing Conference, 2004

SoC design of Ogg Vorbis decoder using embedded processor.
Proceedings of the First Conference on Computing Frontiers, 2004

2003
Embedded implementation of acoustic field enhancement for stereo sound sources.
IEEE Trans. Consumer Electron., 2003

Single DSP Implementation of Realtime 3D Sound Synthesis Algorithm.
J. Circuits Syst. Comput., 2003

Interactive interface of realtime 3D sound movement for embedded applications.
Proceedings of the 2003 International Symposium on Circuits and Systems, 2003

Real-time face object extraction for video phone.
Proceedings of the 2003 International Conference on Image Processing, 2003

2002
Design of Embedded System for Video Coding with Logic-Enhanced DRAM and Configurable Process.
Proceedings of the 10th IEEE International Workshop on Memory Technology, 2002

VLSI architecture of digital matched filter and prime interleaver for W-CDMA.
Proceedings of the 2002 International Symposium on Circuits and Systems, 2002

Error correction block based ARQ protocol for wireless digital video transmission.
Proceedings of the 2002 International Symposium on Circuits and Systems, 2002

OCEAN: Object Communication Environment for Arbitrary Network.
Proceedings of the 22nd International Conference on Distributed Computing Systems, 2002

Parasitic capacitance modeling for multilevel interconnects.
Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems 2002, 2002

Embedded implementation of acoustic field enhancement for stereo headphones.
Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems 2002, 2002

Realtime face object extraction algorithm for video phone.
Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems 2002, 2002

2001
Spatiotemporal segmentation for compact video representation.
Signal Process. Image Commun., 2001

VLSI architecture of dynamically reconfigurable hardware-based cipher.
Proceedings of the 2001 International Symposium on Circuits and Systems, 2001

High Performance Java Hardware Engine and Software Kernel for Embedded Systems.
Proceedings of the SOC Design Methodologies, 2001

Evaluation of processor code efficiency for embedded systems.
Proceedings of the 15th international conference on Supercomputing, 2001

Realtime wavelet video coder based on reduced memory accessing.
Proceedings of ASP-DAC 2001, 2001

A dynamically reconfigurable hardware-based cipher chip.
Proceedings of ASP-DAC 2001, 2001

2000
VLSI Implementation of a Reduced Memory Bandwidth Realtime EZW Video Coder.
Proceedings of the 2000 International Conference on Image Processing, 2000

Layout generation of array cell for NMOS 4-phase dynamic logic (short paper).
Proceedings of ASP-DAC 2000, 2000

1999
An architecture of a matrix-vector multiplier dedicated to video decoding and three-dimensional computer graphics.
IEEE Trans. Circuits Syst. Video Technol., 1999

A wireless data processing system constructed of SAW-devices and its applications to medical cares.
Proceedings of the IEEE-EURASIP Workshop on Nonlinear Signal and Image Processing (NSIP'99), 1999

Recursive maximum likelihood decoder for high-speed satellite communication.
Proceedings of the 1999 International Symposium on Circuits and Systems, ISCAS 1999, Orlando, Florida, USA, May 30, 1999

Hybrid media-processor core for natural and synthetic video decoding.
Proceedings of the 1999 International Symposium on Circuits and Systems, ISCAS 1999, Orlando, Florida, USA, May 30, 1999

FeRAM Circuit Technology for System on a Chip.
Proceedings of the 1st NASA / DoD Workshop on Evolvable Hardware (EH '99), 1999

1998
A layout approach to monolithic microwave IC.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1998

A low-power DSP core architecture for low bitrate speech codec.
Proceedings of the 1998 IEEE International Conference on Acoustics, 1998

An adaptive quantization algorithm for MPEG-2 video coding.
Proceedings of the 1998 IEEE International Conference on Acoustics, 1998

Low-Power Implementation of H.324 Audiovisual Codec Dedicated to Mobile Computing.
Proceedings of the ASP-DAC '98, 1998

1997
ASK digital demodulation scheme for noise immune infrared data communication.
Wirel. Networks, 1997

A Low Power Receiver Architecture for 4 Mbps Infrared Wireless Communication.
J. Circuits Syst. Comput., 1997

Single Chip Implementation of Encoder-Decoder for Low Bit Rate Visual Communication.
J. Circuits Syst. Comput., 1997

An object code compression approach to embedded processors.
Proceedings of the 1997 International Symposium on Low Power Electronics and Design, 1997

Low power architecture for high speed infrared wireless communication system.
Proceedings of the 1997 International Symposium on Low Power Electronics and Design, 1997

Low-power H.263 video CoDec dedicated to mobile computing.
Proceedings of the 1997 International Symposium on Low Power Electronics and Design, 1997

A high performance FIR filter dedicated to digital video transmission.
Proceedings of the ASP-DAC '97 Asia and South Pacific Design Automation Conference, 1997

1996
Automatic layout recycling based on layout description and linear programming.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1996

1995
VLSI implementation of inverse discrete cosine transformer and motion compensator for MPEG2 HDTV video decoding.
IEEE Trans. Circuits Syst. Video Technol., 1995

Optimal Scheduling for Conditional Recource Sharing.
Proceedings of the 1995 IEEE International Symposium on Circuits and Systems, ISCAS 1995, Seattle, Washington, USA, April 30, 1995

Synthesis and simulation of digital demodulator for infrared data communication.
Proceedings of the 1995 Conference on Asia Pacific Design Automation, Makuhari, Massa, Chiba, Japan, August 29, 1995

A design of high-performance multiplier for digital video transmission.
Proceedings of the 1995 Conference on Asia Pacific Design Automation, Makuhari, Massa, Chiba, Japan, August 29, 1995

A layout approach to Monolithic Microwave IC.
Proceedings of the 1995 Conference on Asia Pacific Design Automation, Makuhari, Massa, Chiba, Japan, August 29, 1995

1994
A New Approach of Fractional-Dimension Based Module Clustering for VLSI Layout.
Proceedings of the 1994 IEEE International Symposium on Circuits and Systems, ISCAS 1994, London, England, UK, May 30, 1994

Multi-Threaded Processor for Image Generation.
Proceedings of the 1994 IEEE International Symposium on Circuits and Systems, ISCAS 1994, London, England, UK, May 30, 1994

1993
Optimal layout recycling based on graph theoretic linear programming approach.
Proceedings of the VLSI 93, 1993

An Algorithm to Eliminate All Complex Triangles in a Maximal Planar Graph for Use in VLSI floorplan.
Proceedings of the Algorithmic Aspects of VLSI Layout, 1993

1992
A distributed routing system for multilayer SOG.
Proceedings of the conference on European design automation, 1992

1991
On area-efficient drawings of rectangular duals for VLSI floor-plan.
Math. Program., 1991

1986
A tree-structured parallel processing system for image generation by ray tracing.
Systems and Computers in Japan, 1986

1983
On the Layering Problem of Multilayer PWB Wiring.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1983

A New Global Router for Gate Array LSIsi.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1983

A Rerouting Scheme for Single-Layer Printed Wiring Boards.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1983

LINKS-1: A Parallel Pipelined Multimicrocomputer System for Image Creation
Proceedings of the 10th Annual Symposium on Computer Architecture, 1983, 1983

1981
A Layout System for the Random Logic Portion of an MOS LSI Chip.
IEEE Trans. Computers, 1981

1980
An Approach to Gate Assignment and Module Placement for Printed Wiring Boards.
IEEE Trans. Computers, 1980

Some comments on permutation layout.
Networks, 1980

An Algorithm to Enumerate All Cutsets of a Graph in Linear Time per Cutset.
J. ACM, 1980

A layout system for the random logic portion of MOS LSI.
Proceedings of the 17th Design Automation Conference, 1980

1978
An approach to gate assignment and module placement for printed wiring boards.
Proceedings of the 15th Design Automation Conference, 1978

1977
A New Algorithm for Generating All the Maximal Independent Sets.
SIAM J. Comput., 1977


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