Masaru Sasago

According to our database, Masaru Sasago authored at least 3 papers between 1987 and 1991.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

1991

A 64-Mb DRAM with meshed power line.

Toshio Yamada, Yoshiro Nakata, Junko Hasegawa, Noriaki Amano, Akinori Shibayama, Masaru Sasago, Naoto Matsuo, Toshiki Yabu, Susumu Matsumoto, Shozo Okada, Michihiro Inoue

IEEE J. Solid State Circuits, November, 1991

Three-dimensional resist process simulator PEACE (photo and electron beam lithography analyzing computer engineering system).

Yoshihiko Hirai, Sadafumi Tomida, Kazushi Ikeda, Masaru Sasago, Masayuki Endo, Sigeru Hayama, Noboru Nomura

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1991

1987

Process Modeling for Photoresist Development and Design of DLR/sd (Double-Layer Resist by a Single Development) Process.

Yoshihiko Hirai, Masaru Sasago, Masayuki Endo, Kiichiro Tsuji, Yojiro Mano

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1987