Masashi Shimanouchi

According to our database1, Masashi Shimanouchi authored at least 9 papers between 2001 and 2016.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of five.

Timeline

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PhD thesis 
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Links

On csauthors.net:

Bibliography

2016
SERDES external loopback test using production parametric-test hardware.
Proceedings of the 2016 IEEE International Test Conference, 2016

2013
Theory, model, and applications of non-Gaussian probability density functions for random jitter/noise with non-white power spectral densities.
Proceedings of the 2013 IEEE International Test Conference, 2013

Advancements in high-speed link modeling and simulation (An invited paper for CICC 2013).
Proceedings of the IEEE 2013 Custom Integrated Circuits Conference, 2013

2009
New modeling methods for bounded Gaussian jitter (BGJ)/noise (BGN) and their applications in jitter/noise estimation/testing.
Proceedings of the 2009 IEEE International Test Conference, 2009

2004
Tester Architecture For The Source Synchronous Bus.
Proceedings of the Proceedings 2004 International Test Conference (ITC 2004), 2004

Timing Accuracy Enhancement by a New Calibration Scheme for Multi-Gbps ATE.
Proceedings of the Proceedings 2004 International Test Conference (ITC 2004), 2004

2003
Periodic Jitter Injection with Direct Time Synthesis by SPPTM ATE for SerDes Jitter Tolerance Test in Production.
Proceedings of the Proceedings 2003 International Test Conference (ITC 2003), Breaking Test Interface Bottlenecks, 28 September, 2003

2002
New Paradigm for Signal Paths in ATE Pin Electronics are Needed for Serialcom Device Testing.
Proceedings of the Proceedings IEEE International Test Conference 2002, 2002

2001
An approach to consistent jitter modeling for various jitter aspects and measurement methods.
Proceedings of the Proceedings IEEE International Test Conference 2001, Baltimore, MD, USA, 30 October, 2001


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