Massoud Masoumi

Orcid: 0000-0002-7240-056X

According to our database1, Massoud Masoumi authored at least 13 papers between 2005 and 2020.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

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In proceedings 
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PhD thesis 
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Links

On csauthors.net:

Bibliography

2020
Novel Hybrid CMOS/Memristor Implementation of the AES Algorithm Robust Against Differential Power Analysis Attack.
IEEE Trans. Circuits Syst. II Express Briefs, 2020

Design and implementation of a ring oscillator-based physically unclonable function on field programmable gate array to enhance electronic security.
Int. J. Electron. Secur. Digit. Forensics, 2020

An Efficient Profiling Attack to Real Codes of PIC16F690 and ARM Cortex-M3.
IEEE Access, 2020

2019
A highly efficient and secure hardware implementation of the advanced encryption standard.
J. Inf. Secur. Appl., 2019

2015
Novel Approach to Protect Advanced Encryption Standard Algorithm Implementation Against Differential Electromagnetic and Power Analysis.
IEEE Trans. Inf. Forensics Secur., 2015

2013
Novel Architecture for Efficient FPGA Implementation of Elliptic Curve Cryptographic Processor Over ${\rm GF}(2^{163})$.
IEEE Trans. Very Large Scale Integr. Syst., 2013

A practical fault induction attack against an FPGA implementation of AES cryptosystem.
Proceedings of the 2013 World Congress on Internet Security, 2013

2011
A new and efficient approach to protect AES against differential power analysis.
Proceedings of the 2011 World Congress on Internet Security, 2011

2010
A Novel and Highly Efficient AES Implementation Robust against Differential Power Analysis
CoRR, 2010

2009
A new and efficient approach for estimating the accurate time-domain response of single and capacitive coupled distributed RC interconnects.
Microelectron. J., 2009

A New and Efficient Approach for High-speed and Very Compact Realization of Secure Hash Algorithm.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2009), 2009

2006
NanoCMOS-Molecular Realization of Rijndael.
Proceedings of the Cryptographic Hardware and Embedded Systems, 2006

2005
Enhancing Performance and Saving Energy in CMOS DCVSL Gates by Using a New Transistor Sizing Algorithm.
Proceedings of the 5th IEEE International Workshop on System-on-Chip for Real-Time Applications (IWSOC 2005), 2005


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