Matt Postiff

According to our database, Matt Postiff authored at least 6 papers between 1997 and 2001.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2001

Compiler and microarchitecture mechanisms for exploiting registers to improve memory performance.

Matt Postiff

PhD thesis, 2001

Integrating superscalar processor components to implement register caching.

Matt Postiff, David A. Greene, Steven E. Raasch, Trevor N. Mudge

Proceedings of the 15th international conference on Supercomputing, 2001

2000

The store-load address table and speculative register promotion.

Matt Postiff, David A. Greene, Trevor N. Mudge

Proceedings of the 33rd Annual IEEE/ACM International Symposium on Microarchitecture, 2000

1999

The limits of instruction level parallelism in SPEC95 applications.

Matthew A. Postiff, David A. Greene, Gary S. Tyson, Trevor N. Mudge

SIGARCH Comput. Archit. News, 1999

Performance Limits of Trace Caches.

Matt Postiff, Gary S. Tyson, Trevor N. Mudge

J. Instr. Level Parallelism, 1999

1997

Design Optimization for High-speed Per-address Two-level Branch Predictors.

I-Cheng K. Chen, Chih-Chieh Lee, Matt Postiff, Trevor N. Mudge

Proceedings of the Proceedings 1997 International Conference on Computer Design: VLSI in Computers & Processors, 1997