Matthew Naylor

According to our database, Matthew Naylor authored at least 29 papers between 2005 and 2024.

Collaborative distances:

• Dijkstra number of three.
• Erdős number of four.

2024

Randomized Testing of RISC-V CPUs Using Direct Instruction Injection.

Alexandre Joannou, Peter Rugg, Jonathan Woodruff, Franz A. Fuchs, Marno van der Maas, Matthew Naylor, Michael Roe, Robert N. M. Watson, Peter G. Neumann, Simon W. Moore

IEEE Des. Test, February, 2024

2023

POETS: An Event-driven Approach to Dissipative Particle Dynamics: Implementing a Massively Compute-intensive Problem on a Novel Hard/Software Architecture.

Andrew D. Brown, Jonathan R. Beaumont, David B. Thomas, Julian C. Shillcock, Matthew Naylor, Graeme M. Bragg, Mark Vousden, Simon W. Moore, Shane T. Fleming

ACM Trans. Parallel Comput., June, 2023

2022

Practical Distributed Implementation of Very Large Scale Petri Net Simulations.

Ashur Rafiev, Jordan Morris, Fei Xia, Alex Yakovlev, Matthew Naylor, Simon W. Moore, David B. Thomas, Graeme M. Bragg, Mark Vousden, Andrew Brown

Trans. Petri Nets Other Model. Concurr., 2022

Synchronization in graph analysis algorithms on the Partially Ordered Event-Triggered Systems many-core architecture.

Ashur Rafiev, Alex Yakovlev, Ghaith Tarawneh, Matthew Naylor, Simon W. Moore, David B. Thomas, Graeme M. Bragg, Mark Vousden, Andrew D. Brown

IET Comput. Digit. Tech., 2022

2021

General hardware multicasting for fine-grained message-passing architectures.

Matthew Naylor, Simon W. Moore, David B. Thomas, Jonathan R. Beaumont, Shane T. Fleming, Mark Vousden, A. Theodore Markettos, Thomas Bytheway, Andrew D. Brown

Proceedings of the 29th Euromicro International Conference on Parallel, 2021

2020

A Scoping Review Identifying the Need for Quality Research on the Use of Virtual Reality in Workplace Settings for Stress Management.

Matthew Naylor, Brad Ridout, Andrew J. Campbell

Cyberpsychology Behav. Soc. Netw., 2020

Rigorous engineering for hardware security: Formal modelling and proof in the CHERI design and implementation process.

Kyndylan Nienhuis, Alexandre Joannou, Thomas Bauereiss, Anthony C. J. Fox, Michael Roe, Brian Campbell, Matthew Naylor, Robert M. Norton, Simon W. Moore, Peter G. Neumann, Ian Stark, Robert N. M. Watson, Peter Sewell

Proceedings of the 2020 IEEE Symposium on Security and Privacy, 2020

Termination detection for fine-grained message-passing architectures.

Matthew Naylor, Simon W. Moore, Andrey Mokhov, David B. Thomas, Jonathan R. Beaumont, Shane T. Fleming, A. Theodore Markettos, Thomas Bytheway, Andrew D. Brown

Proceedings of the 31st IEEE International Conference on Application-specific Systems, 2020

2019

Augmented Experiences: Investigating the Feasibility of Virtual Reality as Part of a Workplace Wellbeing Intervention.

Matthew Naylor, Ben W. Morrison, Brad Ridout, Andrew J. Campbell

Interact. Comput., 2019

POETS: Distributed Event-Based Computing - Scaling Behaviour.

Andrew D. Brown, Mark Vousden, Alex Rast, Graeme M. Bragg, David B. Thomas, Jonny Beaumont, Matthew Naylor, Andrey Mokhov

Proceedings of the Parallel Computing: Technology Trends, 2019

Tinsel: A Manythread Overlay for FPGA Clusters.

Matthew Naylor, Simon W. Moore, David B. Thomas

Proceedings of the 29th International Conference on Field Programmable Logic and Applications, 2019

2017

Distributed Event-Based Computing.

Andrew D. Brown, David B. Thomas, Jeff Reeve, Ghaith Tarawneh, Alessandro de Gennaro, Andrey Mokhov, Matthew Naylor, Tom Kazmierski

Proceedings of the Parallel Computing is Everywhere, 2017

Programming Model to Develop Supercomputer Combinatorial Solvers.

Ghaith Tarawneh, Andrey Mokhov, Matthew Naylor, Alex Rast, Simon W. Moore, David B. Thomas, Alex Yakovlev, Andrew D. Brown

Proceedings of the 46th International Conference on Parallel Processing Workshops, 2017

2016

A consistency checker for memory subsystem traces.

Matthew Naylor, Simon W. Moore, Alan Mujumdar

Proceedings of the 2016 Formal Methods in Computer-Aided Design, 2016

2015

A generic synthesisable test bench.

Matthew Naylor, Simon W. Moore

Proceedings of the 13. ACM/IEEE International Conference on Formal Methods and Models for Codesign, 2015

2014

Adapting FreeRTOS for multicores: an experience report.

James Mistry, Matthew Naylor, Jim Woodcock

Softw. Pract. Exp., 2014

Rapid codesign of a soft vector processor and its compiler.

Matthew Naylor, Simon W. Moore

Proceedings of the 24th International Conference on Field Programmable Logic and Applications, 2014

2013

Managing the FPGA memory wall: Custom computing or vector processing?

Matthew Naylor, Paul James Fox, A. Theodore Markettos, Simon W. Moore

Proceedings of the 23rd International Conference on Field programmable Logic and Applications, 2013

A spiking neural network on a portable FPGA tablet.

Matthew Naylor, Paul James Fox, A. Theodore Markettos, Simon W. Moore

Proceedings of the 23rd International Conference on Field programmable Logic and Applications, 2013

2012

The Reduceron reconfigured and re-evaluated.

Matthew Naylor, Colin Runciman

J. Funct. Program., 2012

Advances in Lazy SmallCheck.

Jason S. Reich, Matthew Naylor, Colin Runciman

Proceedings of the Implementation and Application of Functional Languages, 2012

2011

Lazy Generation of Canonical Test Programs.

Jason S. Reich, Matthew Naylor, Colin Runciman

Proceedings of the Implementation and Application of Functional Languages, 2011

2010

The reduceron reconfigured.

Matthew Naylor, Colin Runciman

Proceedings of the Proceeding of the 15th ACM SIGPLAN international conference on Functional programming, 2010

2009

Expressible sharing for functional circuit description.

Matthew Naylor, Colin Runciman

High. Order Symb. Comput., 2009

2008

Smallcheck and lazy smallcheck: automatic exhaustive testing for small values.

Colin Runciman, Matthew Naylor, Fredrik Lindblad

Proceedings of the 1st ACM SIGPLAN Symposium on Haskell, 2008

2007

Finding Inputs that Reach a Target Expression.

Matthew Naylor, Colin Runciman

Proceedings of the Seventh IEEE International Workshop on Source Code Analysis and Manipulation (SCAM 2007), September 30, 2007

The Reduceron: Widening the von Neumann Bottleneck for Graph Reduction Using an FPGA.

Matthew Naylor, Colin Runciman

Proceedings of the Implementation and Application of Functional Languages, 2007

A functional-logic library for wired.

Matthew Naylor, Emil Axelsson, Colin Runciman

Proceedings of the ACM SIGPLAN Workshop on Haskell, 2007

2005

Pixel Behaviour Metrics for Dynamic Background Modelling with the Projected Difference Pattern Method.

Peter Pakulski, Karl Sammut, Fangpo He, Matthew Naylor

Proceedings of the International Conference on Digital Image Computing: Techniques and Applications, 2005