Matthew Naylor

According to our database1, Matthew Naylor authored at least 21 papers between 2005 and 2019.

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Timeline

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Bibliography

2019
Augmented Experiences: Investigating the Feasibility of Virtual Reality as Part of a Workplace Wellbeing Intervention.
Interact. Comput., 2019

POETS: Distributed Event-Based Computing - Scaling Behaviour.
Proceedings of the Parallel Computing: Technology Trends, 2019

Tinsel: A Manythread Overlay for FPGA Clusters.
Proceedings of the 29th International Conference on Field Programmable Logic and Applications, 2019

2017
Distributed Event-Based Computing.
Proceedings of the Parallel Computing is Everywhere, 2017

Programming Model to Develop Supercomputer Combinatorial Solvers.
Proceedings of the 46th International Conference on Parallel Processing Workshops, 2017

2016
A consistency checker for memory subsystem traces.
Proceedings of the 2016 Formal Methods in Computer-Aided Design, 2016

2015
A generic synthesisable test bench.
Proceedings of the 13. ACM/IEEE International Conference on Formal Methods and Models for Codesign, 2015

2014
Adapting FreeRTOS for multicores: an experience report.
Softw. Pract. Exp., 2014

Rapid codesign of a soft vector processor and its compiler.
Proceedings of the 24th International Conference on Field Programmable Logic and Applications, 2014

2013
Managing the FPGA memory wall: Custom computing or vector processing?
Proceedings of the 23rd International Conference on Field programmable Logic and Applications, 2013

A spiking neural network on a portable FPGA tablet.
Proceedings of the 23rd International Conference on Field programmable Logic and Applications, 2013

2012
The Reduceron reconfigured and re-evaluated.
J. Funct. Program., 2012

Advances in Lazy SmallCheck.
Proceedings of the Implementation and Application of Functional Languages, 2012

2011
Lazy Generation of Canonical Test Programs.
Proceedings of the Implementation and Application of Functional Languages, 2011

2010
The reduceron reconfigured.
Proceedings of the Proceeding of the 15th ACM SIGPLAN international conference on Functional programming, 2010

2009
Expressible sharing for functional circuit description.
High. Order Symb. Comput., 2009

2008
Smallcheck and lazy smallcheck: automatic exhaustive testing for small values.
Proceedings of the 1st ACM SIGPLAN Symposium on Haskell, 2008

2007
Finding Inputs that Reach a Target Expression.
Proceedings of the Seventh IEEE International Workshop on Source Code Analysis and Manipulation (SCAM 2007), September 30, 2007

The Reduceron: Widening the von Neumann Bottleneck for Graph Reduction Using an FPGA.
Proceedings of the Implementation and Application of Functional Languages, 2007

A functional-logic library for wired.
Proceedings of the ACM SIGPLAN Workshop on Haskell, 2007

2005
Pixel Behaviour Metrics for Dynamic Background Modelling with the Projected Difference Pattern Method.
Proceedings of the International Conference on Digital Image Computing: Techniques and Applications, 2005


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