Mehdi Ehsanian

According to our database1, Mehdi Ehsanian authored at least 10 papers between 1996 and 2020.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

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Article 
PhD thesis 
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Links

On csauthors.net:

Bibliography

2020
Generalized Method for Extraction of Offset, Gain, and Timing Skew Errors in Time-Interleaved ADCs.
IEEE Trans. Circuits Syst. II Express Briefs, 2020

2017
An Improved KFCM Clustering Method Used for Multiple Fault Diagnosis of Analog Circuits.
Circuits Syst. Signal Process., 2017

A linear high capture range CDR with adaptive loop bandwidth for SONET application.
Proceedings of the 29th International Conference on Microelectronics, 2017

An FPGA based DPLL with fuzzy logic controllable loop filters.
Proceedings of the 29th International Conference on Microelectronics, 2017

2016
Highly phase-linear self-biased CMOS IR-UWB LNA with Sub-ps group-delay variations.
Proceedings of the 28th International Conference on Microelectronics, 2016

2014
A widebound low phase noise LC-VCO based PLL with automatic amplitude control.
Proceedings of the 26th International Conference on Microelectronics, 2014

Low-power burst-mode clock recovery circuit using analog phase interpolator.
Proceedings of the 26th International Conference on Microelectronics, 2014

Self-biased resistive-feedback current-reused CMOS UWB LNA with 1.7dB nf for IR-UWB applications.
Proceedings of the 26th International Conference on Microelectronics, 2014

2008
Test and validation of a non-deterministic system - True Random Number Generator.
Proceedings of the IEEE International High Level Design Validation and Test Workshop, 2008

1996
A new digital test approach for analog-to-digital converter testing.
Proceedings of the 14th IEEE VLSI Test Symposium (VTS'96), April 28, 1996


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