Michael A. Shanblatt

Affiliations:
  • Michigan State University, East Lansing, MI, USA


According to our database1, Michael A. Shanblatt authored at least 29 papers between 1986 and 2007.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

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Bibliography

2007
A Paradigm of Government/Industry/University Cooperation: A PSoC Controller for a NASA Robotic Arm.
Proceedings of the IEEE International Conference on Microelectronic Systems Education, 2007

2005
A Simulink-to-FPGA Implementation Tool for Enhanced Design Flow.
Proceedings of the 2005 International Conference on Microelectronics Systems Education, 2005

2004
A Multi-objective Approach to Configuring Embedded System Architectures.
Proceedings of the Genetic and Evolutionary Computation, 2004

2003
A University-based Web Resource Supporting the Xilinx University Program.
Proceedings of the 2003 International Conference on Microelectronics Systems Education, 2003

An Evolutionary Approach to Configuring an Embedded System Based on Power Consumption.
Proceedings of the 3rd IEEE International Workshop on System-on-Chip for Real-Time Applications (IWSOC'03), 30 June, 2003

Evaluation of Parameter Sensitivity for Portable Embedded Systems through Evolutionary Techniques.
Proceedings of the Genetic and Evolutionary Computation, 2003

2001
A University-Based Support Environment for the Xilinx University Program.
Proceedings of the 2001 International Conference on Microelectronics Systems Education, 2001

1999
Reducing BDD Size by Exploiting Structural Connectivity.
Proceedings of the 9th Great Lakes Symposium on VLSI (GLS-VLSI '99), 1999

1998
Mapping Multiplication Algorithms into a Family of LUT-based FPGAs (Abstract).
Proceedings of the 1998 ACM/SIGDA Sixth International Symposium on Field Programmable Gate Arrays, 1998

1995
Architecture and statistical model of a pulse-mode digital multilayer neural network.
IEEE Trans. Neural Networks, 1995

Random noise effects in pulse-mode digital multilayer neural networks.
IEEE Trans. Neural Networks, 1995

Human-like dynamic programming neural networks for dynamic time warping speech recognition.
Int. J. Neural Syst., 1995

1993
A VLSI-based digital multilayer neural network architecture.
Proceedings of the Third Great Lakes Symposium on Design Automation of High Performance VLSI Systems, 1993

1992
A two-phase optimization neural network.
IEEE Trans. Neural Networks, 1992

Linear and quadratic programming neural network analysis.
IEEE Trans. Neural Networks, 1992

1991
Energy function analysis of dynamic programming neural networks.
IEEE Trans. Neural Networks, 1991

Improved Neural Networks For Linear and Nonlinear Programming.
Int. J. Neural Syst., 1991

An architecture design using VLSI building blocks for dynamic programming neural networks.
Proceedings of the First Great Lakes Symposium on VLSI, 1991

1990
An Artificial Neural Network Algorithm for Dynamic Programming.
Int. J. Neural Syst., 1990

Stability of linear programming neural network for problems with hypercube feasible region.
Proceedings of the IJCNN 1990, 1990

1988
A conceptual framework for ASIC design.
Proc. IEEE, 1988

A conceptual framework for designing robotic computational hardware with ASIC technology.
Proceedings of the 1988 IEEE International Conference on Robotics and Automation, 1988

Computer architecture design for robotics.
Proceedings of the 1988 IEEE International Conference on Robotics and Automation, 1988

1987
Real-time DKS on a single chip.
IEEE J. Robotics Autom., 1987

Systematic Generation and Enumeration of Systolic Arrays from Algorithms.
Proceedings of the International Conference on Parallel Processing, 1987

A Conceptual Framework for Designing ASIC Hardware.
Proceedings of the 24th ACM/IEEE Design Automation Conference. Miami Beach, FL, USA, June 28, 1987

An Improved Systematic Method for Constructing Systolic Arrays from Algorithms.
Proceedings of the 24th ACM/IEEE Design Automation Conference. Miami Beach, FL, USA, June 28, 1987

1986
Real-Time Direct Kinematics on a VLSI Chip.
Proceedings of the 7th IEEE Real-Time Systems Symposium (RTSS '86), 1986

A VLSI chip architecture for the real-time computation of direct kinematics.
Proceedings of the 1986 IEEE International Conference on Robotics and Automation, 1986


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