Chin-Long Wey

According to our database1, Chin-Long Wey authored at least 122 papers between 1985 and 2019.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Awards

IEEE Fellow

IEEE Fellow 2011, "For leadership in education and services in integrated circuits".

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Dataset
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Links

On csauthors.net:

Bibliography

2019
Machine Learning Classification for Assessing the Degree of Stenosis and Blood Flow Volume at Arteriovenous Fistulas of Hemodialysis Patients Using a New Photoplethysmography Sensor Device.
Sensors, 2019

Quality Evaluation via PPG on the AVFs of Hemodialysis Patients Based on Both Blood Flow Volume and Degree of Stenosis.
Proceedings of the 2019 IEEE SENSORS, Montreal, QC, Canada, October 27-30, 2019, 2019

2018
A Portable, Wireless Photoplethysomography Sensor for Assessing Health of Arteriovenous Fistula Using Class-Weighted Support Vector Machine.
Sensors, 2018

Design and Implementation of OLED Driving and OPD Readout Circuitry for an Optical Vibration Sensor.
Proceedings of the 2018 IEEE SENSORS, New Delhi, India, October 28-31, 2018, 2018

2017
PACES: A Partition-Centering-Based Symmetry Placement for Binary-Weighted Unit Capacitor Arrays.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2017

2.3 A single-inductor dual-output converter with linear-amplifier-driven cross regulation for prioritized energy-distribution control of envelope-tracking supply modulator.
Proceedings of the 2017 IEEE International Solid-State Circuits Conference, 2017

20.2 Digital low-dropout regulator with anti PVT-variation technique for dynamic voltage scaling and adaptive voltage scaling multicore processor.
Proceedings of the 2017 IEEE International Solid-State Circuits Conference, 2017

10.5 A three-level single-inductor triple-output converter with an adjustable flying-capacitor technique for low output ripple and fast transient response.
Proceedings of the 2017 IEEE International Solid-State Circuits Conference, 2017

A new reflective PPG LED-PD sensor module for cuffless blood pressure measurement at wrist artery.
Proceedings of the 2017 IEEE SENSORS, Glasgow, United Kingdom, October 29, 2017

Live demonstration: A novel cuffless photoplethysmography sensor for continuous blood pressure measurement.
Proceedings of the 2017 IEEE SENSORS, Glasgow, United Kingdom, October 29, 2017

A low quiescent current and cross regulation single-inductor dual-output converter with stacking MOSFET driving technique.
Proceedings of the 43rd IEEE European Solid State Circuits Conference, 2017

Unsymmetrical parallel switched-capacitor (UP-SC) regulator with fast searching optimum ratio technique.
Proceedings of the 43rd IEEE European Solid State Circuits Conference, 2017

2016
Multiplication of a Constant (2k ± 1) and Its Fast Hardware Implementation.
J. Signal Process. Syst., 2016

95% light-load efficiency single-inductor dual-output DC-DC buck converter with synthesized waveform control technique for USB type-C.
Proceedings of the 2016 IEEE Symposium on VLSI Circuits, 2016

12.7 A 96%-efficiency and 0.5%-current-cross-regulation single-inductor multiple floating-output LED driver with 24b color resolution.
Proceedings of the 2016 IEEE International Solid-State Circuits Conference, 2016

A new cuffless optical sensor for blood pressure measuring with self-adaptive signal processing.
Proceedings of the 2016 IEEE SENSORS, Orlando, FL, USA, October 30 - November 3, 2016, 2016

Lossless inductor current control in envelope tracking supply modulator with self-allocation of energy for optimzation of efficiency and EVM.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2016

Ultra-low voltage ripple in DC-DC boost converter by the pumping capacitor and wire inductance technique.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2016

93% Efficiency and 0.99 power factor in pseudo-linear LED driver.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2016

A digital low-dropout-regulator with steady-state load current (SLC) estimator and dynamic gain scaling (DGS) control.
Proceedings of the 2016 IEEE Asia Pacific Conference on Circuits and Systems, 2016

2015
Performance-Driven Unit-Capacitor Placement of Successive-Approximation-Register ADCs.
ACM Trans. Design Autom. Electr. Syst., 2015

Efficient Algorithm and Fast Hardware Implementation for Multiply-by-(1+2<sup>k</sup>).
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2015

12.6 90% Peak efficiency single-inductor-multiple-output DC-DC buck converter with output independent gate drive control.
Proceedings of the 2015 IEEE International Solid-State Circuits Conference, 2015

120V/ns output slew rate enhancement technique and high voltage clamping circuit in high integrated gate driver for power GaN FETs.
Proceedings of the ESSCIRC Conference 2015, 2015

Suppressing output overshoot voltage technique with 47.1mW/μs power-recycling rate and 93% peak efficiency DC-DC converter for multi-core processors.
Proceedings of the ESSCIRC Conference 2015, 2015

Pseudo AC current synthesizer and DC offset-corrected technique in constant-on-time control buck converter for werable electronics.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2015

200nA low quiescent current deep-standby mode in 28nm DC-DC buck converter for active implantable medical devices.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2015

2014
Fast Charging and High Efficiency Switching-Based Charger With Continuous Built-In Resistance Detection and Automatic Energy Deliver Control for Portable Electronics.
IEEE J. Solid State Circuits, 2014

A Switchable Digital-Analog Low-Dropout Regulator for Analog Dynamic Voltage Scaling Technique.
IEEE J. Solid State Circuits, 2014

Efficient Multiply-by-3 and Divide-by-3 Algorithms and Their Fast Hardware Implementation.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2014

A direct AC-DC and DC-DC cross-source energy harvesting circuit with analog iterating-based MPPT technique with 72.5% conversion efficiency and 94.6% tracking efficiency.
Proceedings of the Symposium on VLSI Circuits, 2014

±3% voltage variation and 95% efficiency 28nm constant on-time controlled step-down switching regulator directly supplying to Wi-Fi systems.
Proceedings of the Symposium on VLSI Circuits, 2014

17.10 0.65V-input-voltage 0.6V-output-voltage 30ppm/°C low-dropout regulator with embedded voltage reference for low-power biomedical systems.
Proceedings of the 2014 IEEE International Conference on Solid-State Circuits Conference, 2014

A dual-level dual-phase pulse-width modulation class-D amplifier with 0.001% THD, 112 dB SNR.
Proceedings of the IEEE International Symposium on Circuits and Systemss, 2014

A Class-D amplifier powered by embedded single-inductor bipolar-output power module with low common noise and dynamic voltage boosting technique.
Proceedings of the ESSCIRC 2014, 2014

Single inductor quad output switching converter with priority-scheduled program for fast transient and unlimited-load range in 40nm CMOS technology.
Proceedings of the ESSCIRC 2014, 2014

Anti-ESL/ESR variation robust constant-on-time control for DC-DC buck converter in 28nm CMOS technology.
Proceedings of the IEEE 2014 Custom Integrated Circuits Conference, 2014

A 20MS/s buck/boost supply modulator for envelope tracking applications with direct digital interface.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2014

2013
Optimal common-centroid-based unit capacitor placements for yield enhancement of switched-capacitor circuits.
ACM Trans. Design Autom. Electr. Syst., 2013

Low-cost parallel FFT processors with conflict-free ROM-based twiddle factor generator for DVB-T2 applications.
Proceedings of the IEEE 56th International Midwest Symposium on Circuits and Systems, 2013

A voltage-mode boost DC-DC converter with a constant-duty-cycle pulse control.
Proceedings of the 4th IEEE Latin American Symposium on Circuits and Systems, 2013

A single-inductor programmable-output (SIPO) DC-DC converter for low power applications.
Proceedings of the IECON 2013, 2013

A unitized charging and discharging smart battery management system.
Proceedings of the International Conference on Connected Vehicles and Expo, 2013

Enhancement of Controller Area Network (CAN) bus arbitration mechanism.
Proceedings of the International Conference on Connected Vehicles and Expo, 2013

2012
A fast hysteretic buck converter with adaptive ripple controller.
Proceedings of the 55th IEEE International Midwest Symposium on Circuits and Systems, 2012

Efficient algorithm and hardware implementation of 3N for arithmetic and for Radix-8 encodings.
Proceedings of the 55th IEEE International Midwest Symposium on Circuits and Systems, 2012

A Fast 64-bit hybrid adder design in 90nm CMOS process.
Proceedings of the 55th IEEE International Midwest Symposium on Circuits and Systems, 2012

Reliable Power Delivery System Design for Three-Dimensional Integrated Circuits (3D ICs).
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2012

Generic Reliability Analysis for Safety-Critical FlexRay Drive-By-Wire Systems.
Proceedings of the 2012 International Conference on Connected Vehicles and Expo, 2012

2011
Programmable System-on-Chip for Silicon Prototyping.
IEEE Trans. Ind. Electron., 2011

A 5.5-GHz 1-mW Full-Modulus-Range Programmable Frequency Divider in 90-nm CMOS Process.
IEEE Trans. Circuits Syst. II Express Briefs, 2011

A Low-Cost Continuous-Flow Parallel Memory-Based FFT Processor for UWB Applications.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2011

Reconfigurable Homogenous Multi-Core FFT Processor Architectures for Hybrid SISO/MIMO OFDM Wireless Communications.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2011

Design Methodology for Yield Enhancement of Switched-Capacitor Analog Integrated Circuits.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2011

Yield-award placement optimization for Switched-Capacitor analog integrated circuits.
Proceedings of the IEEE 24th International SoC Conference, SOCC 2011, Taipei, Taiwan, 2011

Design of ultra-wide-load, high-efficient DC-DC buck converters.
Proceedings of the 18th IEEE International Conference on Electronics, Circuits and Systems, 2011

2010
Low-cost FFT processor for DVB-T2 applications.
IEEE Trans. Consumer Electron., 2010

A Transceiver Front End for Electronic Control Units in FlexRay-Based Automotive Communication Systems.
IEEE Trans. Circuits Syst. I Regul. Pap., 2010

Placement Optimization for Yield Improvement of Switched-Capacitor Analog Integrated Circuits.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2010

An effective phase detector for phase-locked loops with wide capture range and fast acquisition time.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2010), May 30, 2010

High-speed and low-power programmable frequency divider.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2010), May 30, 2010

2009
An Edge Missing Compensator for Fast Settling Wide Locking Range Phase-Locked Loops.
IEEE J. Solid State Circuits, 2009

Robustness investigation of the FlexRay system.
Proceedings of the IEEE Fourth International Symposium on Industrial Embedded Systems, 2009

An edge-missing compensator for fast-settling wide-locking-range PLLs.
Proceedings of the IEEE International Solid-State Circuits Conference, 2009

Yield evaluation of analog placement with arbitrary capacitor ratio.
Proceedings of the 10th International Symposium on Quality of Electronic Design (ISQED 2009), 2009

Implementation and Prototyping of a Complex Multi-project System-on-a-chip.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2009), 2009

2008
Algorithms of Finding the First Two Minimum Values and Their Hardware Implementation.
IEEE Trans. Circuits Syst. I Regul. Pap., 2008

Impact of Capacitance Correlation on Yield Enhancement of Mixed-Signal/Analog Integrated Circuits.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2008

PrSoC: Programmable System-on-chip (SoC) for silicon prototyping.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2008), 2008

A low-cost continuous flow parallel memory-based FFT processor for Ultra-Wideband (UWB) applications.
Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems, 2008

Design of square generator with small look-up table.
Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems, 2008

2007
Design of cost-efficient memory-based FFT processors using single-port memories.
Proceedings of the 2007 IEEE International SOC Conference, 2007

Efficient VLSI Implementation of Memory-Based FFT Processors for DVB-T Applications.
Proceedings of the 2007 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2007), 2007

High-speed, Low Cost Parallel Memory-Based FFT Processors for OFDM Applications.
Proceedings of the 14th IEEE International Conference on Electronics, 2007

2006
Compressed domain content-based retrieval of MP3 audio example using quantization tree indexing and melody-line tracking method.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006

Design of Reliable CMOS Phase-Locked Loops.
Proceedings of the 13th IEEE International Conference on Electronics, 2006

2005
Reliability enhancement of CMOS SRAMs.
Proceedings of the 13th IEEE International Workshop on Memory Technology, 2005

A novel reconfigurable architecture of low-power unsigned multiplier for digital signal processing.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005

Design of a CMOS Operational Amplifier Amenable to Extreme Voltage Stress.
Proceedings of the 20th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2005), 2005

An Efficient Transparent Test Scheme for Embedded Word-Oriented Memories.
Proceedings of the 2005 Design, 2005

Design of a CMOS Operational Amplifier for Extreme-Voltage Stress Test.
Proceedings of the 14th Asian Test Symposium (ATS 2005), 2005

2004
Hierarchical extreme-voltage stress test of analog CMOS ICs for gate-oxide reliability enhancement.
Proceedings of the 14th ACM Great Lakes Symposium on VLSI 2004, 2004

A noise optimization technique for codesign of CMOS radio-frequency low noise amplifiers and low-quality spiral inductors.
Proceedings of the 14th ACM Great Lakes Symposium on VLSI 2004, 2004

Burn-In Stress Test of Analog CMOS ICs.
Proceedings of the 13th Asian Test Symposium (ATS 2004), 2004

2001
High-Voltage Stress Test Paradigms of Analog CMOS ICs for Gate-Oxide Reliability Enhancement.
Proceedings of the 19th IEEE VLSI Test Symposium (VTS 2001), Test and Diagnosis in a Nanometric World, 29 April, 2001

Extreme-voltage stress vector generation of analog CMOS ICs for gate-oxide reliability enhancement.
Proceedings of the Proceedings IEEE International Test Conference 2001, Baltimore, MD, USA, 30 October, 2001

2000
A fully differential current copier for performance improvement.
Int. J. Circuit Theory Appl., 2000

Mixed-Signal SoC Testing: Is Mixed-Signal Design-for-Test on Its Way.
Proceedings of the 9th Asian Test Symposium (ATS 2000), 4-6 December 2000, Taipei, Taiwan, 2000

1998
ATPRG: an automatic test program generator using HDL-A for fault diagnosis of analog/mixed-signal integrated circuits.
IEEE Trans. Instrum. Meas., 1998

Design of a High-Speed Square Generator.
IEEE Trans. Computers, 1998

Fault macromodel for switches in switched-current circuits.
Int. J. Circuit Theory Appl., 1998

Diagnosability analysis of analogue circuits.
Int. J. Circuit Theory Appl., 1998

High-speed CMOS switched-current D/A converters for low-power/low-voltage signal processing applications.
Proceedings of the 5th IEEE International Conference on Electronics, Circuits and Systems, 1998

Test points selection process and diagnosability analysis of analog integrated circuits.
Proceedings of the International Conference on Computer Design: VLSI in Computers and Processors, 1998

Mapping Multiplication Algorithms into a Family of LUT-based FPGAs (Abstract).
Proceedings of the 1998 ACM/SIGDA Sixth International Symposium on Field Programmable Gate Arrays, 1998

1997
Development of Hierarchical Testability Design Methodologies for Analog/Mixed-Signal Integrated Circuits.
Proceedings of the Proceedings 1997 International Conference on Computer Design: VLSI in Computers & Processors, 1997

1996
Built-in self-test (BIST) design of high-speed carry-free dividers.
IEEE Trans. Very Large Scale Integr. Syst., 1996

Mixed-signal circuit testing-A review.
Proceedings of Third International Conference on Electronics, Circuits, and Systems, 1996

On Design of Efficient Square Generator.
Proceedings of the 1996 International Conference on Computer Design (ICCD '96), 1996

Test Generation Of Analog Switched-Current Circuits.
Proceedings of the 5th Asian Test Symposium (ATS '96), 1996

1995
Test generation and concurrent error detection in current-mode A/D converters.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1995

Application of Bipartite Graphs for Achieving Race-Free State Assignment.
IEEE Trans. Computers, 1995

Simple yet accurate current copiers for low-voltage current-mode signal-processing applications.
Int. J. Circuit Theory Appl., 1995

A self-timed redundant-binary number to binary number converter for digital arithmetic processors.
Proceedings of the 1995 International Conference on Computer Design (ICCD '95), 1995

High-radix SRT division with speculation of quotient digits .
Proceedings of the 1995 International Conference on Computer Design (ICCD '95), 1995

1994
Concurrent Error Detection in High Speed Carry-free Division Using Alternative Input Data.
Proceedings of the Proceedings 1994 IEEE International Conference on Computer Design: VLSI in Computer & Processors, 1994

1993
An accurate reference-generating circuit for successive approximation current mode A/D converters.
Int. J. Circuit Theory Appl., 1993

Race-free state assignments using bipartite graphs.
Proceedings of the 1993 IEEE International Symposium on Circuits and Systems, 1993

ASLCScan: A Scan Design Technique for Asynchronous Sequential Logic Circuits.
Proceedings of the Proceedings 1993 International Conference on Computer Design: VLSI in Computers & Processors, 1993

1991
Concurrent Error Detection in Array Dividers by Alternating Input Data.
Proceedings of the Proceedings 1991 IEEE International Conference on Computer Design: VLSI in Computer & Processors, 1991

1990
An efficient output phase assignment for PLA minimization.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1990

Design of repairable and fully testable folded PLAs.
Proceedings of the 1990 IEEE International Conference on Computer Design: VLSI in Computers and Processors, 1990

Design of Repairable and Fully Diagnosable Folded PLAs for Yield Enhancement.
Proceedings of the 27th ACM/IEEE Design Automation Conference. Orlando, 1990

1989
Fault Location in Repairable Programmable Logic Arrays.
Proceedings of the Proceedings International Test Conference 1989, 1989

OPAM: an efficient output phase assignment for multilevel logic minimization.
Proceedings of the Computer Design: VLSI in Computers and Processors, 1989

1988
On yield consideration for the design of redundant programmable logic arrays.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1988

The design of concurrent error diagnosable systolic arrays for band matrix multiplications.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1988

Test generation of C-testable array dividers.
Proceedings of the Computer Design: VLSI in Computers and Processors, 1988

PLAYGROUND: Minimization of PLAs with Mixed Ground True Outputs.
Proceedings of the 25th ACM/IEEE Conference on Design Automation, 1988

1987
On the Repair of Redundant RAM's.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1987

On a Novel Self-Test Approach to Digital Testing.
Comput. J., 1987

1985
On a Multiprocessor System with Dynamic Redundancy.
Proceedings of the 6th IEEE Real-Time Systems Symposium (RTSS '85), 1985


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