Michio Yokoyama

Orcid: 0000-0003-2837-6272

According to our database1, Michio Yokoyama authored at least 17 papers between 2003 and 2023.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

Legend:

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PhD thesis 
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Online presence:

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Bibliography

2023
Stress Data Collection and Analysis Using "Mind Scale" with the Post-Covid World.
Proceedings of the IEEE International Conference on Consumer Electronics, 2023

Stress Data Collection and Analysis using "MindScale" for Stress Visualization.
Proceedings of the 12th IEEE Global Conference on Consumer Electronics, 2023

The Pillow-Type Unrestrained Heart Rate Measurement System for Sleep-State Analysis.
Proceedings of the 12th IEEE Global Conference on Consumer Electronics, 2023

2021
Evaluation of a Filter-less AD-PLL with a Wide Input Frequency Range Using a Fast-Locking Algorithm.
Proceedings of the 28th IEEE International Conference on Electronics, 2021

2020
Changing Tendency Analysis of Sleep Quality on the Basis of Temperature and Respiratory Frequency Using a Neural Network Model.
Int. J. Fuzzy Log. Intell. Syst., 2020

2018
Estimation System of Blood Pressure Variation with Photoplethysmography Signals Using Multiple Regression Analysis and Neural Network.
Int. J. Fuzzy Log. Intell. Syst., 2018

Flexible and Printable Phase Shifter with Polymer Actuator for 12-GHz Band.
IEICE Trans. Electron., 2018

2015
SPICE model of memristive device using Tukey window function.
IEICE Electron. Express, 2015

2013
Design of low-power clock generator synchronized with AC power for adiabatic dynamic CMOS logic.
IEICE Electron. Express, 2013

2012
Design of the ultra low-power synchronizer using ADCL buffer for adiabatic logic.
IEICE Electron. Express, 2012

Power-saving analysis of adiabatic logic in subthreshold region.
Proceedings of the International Symposium on Intelligent Signal Processing and Communications Systems, 2012

2PCDAL: Two-phase clocking dual-rail adiabatic logic.
Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems, 2012

2007
VLSI Implementation of a 4 x 4-bit Multiplier in a Two Phase Drive Adiabatic Dynamic CMOS Logic.
IEICE Trans. Electron., 2007

A 70 MHz Multiplierless FIR Hilbert Transformer in 0.35 µm Standard CMOS Library.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2007

2006
2PADCL: Two Phase drive Adiabatic Dynamic CMOS Logic.
Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems 2006, 2006

2005
New cost-effective VLSI implementation of multiplierless FIR filter using common subexpression elimination.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005

2003
Carry Propagation Free Adder/Subtracter Using Adiabatic Dynamic CMOS Logic Circuit Technology.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2003


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