Minseong Lee

According to our database, Minseong Lee authored at least 3 papers between 2024 and 2025.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of five.

2025

Demonstration of Logic-Block Performance-Power-Area Gain by 1^st Generation Back Side Power Delivery Network for SoC and HPC Applications Beyond 2 nm Node.

H. Fukutome, J. Kim, Joonghan Shin, J. Kim, Youngsoo Lee, S. Chae, B. Eom, Y. S. Nam, Minseong Lee, Sanghyun Ha, E. G. Chung, Sung-Hoon Lee, Sang Kim, K. H. Cho, K. W. Lee, D. W. Kim, H.-J. Cho, K. Rim, J. Song

Proceedings of the IEEE Custom Integrated Circuits Conference, 2025

2024

Product Performance Aware 3^rd Generation GAA Platform Transistor Design with Extreme Small Local Layout Effect and Transistor Variation.

Dongchan Jeong, Seungkwon Kim, Seulki Park, Sanghyeon Lee, Sada-Aki Masuoka, Byungha Choi, Shincheol Min, Sanghoon Lee, Minseong Lee, Chang-Woo Sohn, Jaehun Jeong, Yuri Yasuda-Masuoka, Ja-Hum Ku

Proceedings of the IEEE Symposium on VLSI Technology and Circuits 2024, 2024

Demonstration of Logic-Block Performance-Power Gain by 1st Generation Back Side Power Delivery Network for SoC and HPC Applications Beyond 2nm Node.

H. Fukutome, J. Kim, Joonghan Shin, Youngsoo Lee, Youngsoo Park, Do-Youn Oh, Seung-Hoon Chae, B. Eom, You Nam, Minseong Lee, Sanghyun Ha, Eun-Ae Chung, Moon-Ho Jo, Sung-Hoon Lee, Sang Kim, Keun Cho, Kyung-Woo Lee, Dong Kim, H. J. Cho, Kwan Rim, SD Kwon, Jun-Ho Song

Proceedings of the IEEE Symposium on VLSI Technology and Circuits 2024, 2024