Miroslav Drozd

According to our database1, Miroslav Drozd authored at least 12 papers between 2011 and 2020.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of five.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Other 

Links

On csauthors.net:

Bibliography

2020
Co-Embedding Additional Security Data and Obfuscating Low-Level FPGA Program Code.
Proceedings of the IEEE East-West Design & Test Symposium, 2020

Using Natural Version Redundancy of FPGA Projects in Area of Critical Applications.
Proceedings of the 11th IEEE International Conference on Dependable Systems, 2020

A method of hidden faults opposition for FPGA-based components of safety-related systems.
Proceedings of The Third International Workshop on Computer Modeling and Intelligent Systems (CMIS-2020), 2020

2019
Sharing of Functional and Special Means in Pipeline Floating-Point Systems with Strongly Connected Versions.
Proceedings of the 10th IEEE International Conference on Intelligent Data Acquisition and Advanced Computing Systems: Technology and Applications, 2019

Power-Oriented Checkability of Matrix and Pipeline Circuits in FPGA-Based Digital Components of Safety-Related Systems.
Proceedings of the 15th International Conference on ICT in Education, 2019

A Method of Common Signal Monitoring in FPGA-Based Components of Safety-Related Systems.
Proceedings of the Second International Workshop on Computer Modeling and Intelligent Systems (CMIS-2019), 2019

2018
Evolution of a Problem of the Hidden Faults in the Digital Components of Safety-Related Systens.
Proceedings of the 2018 IEEE East-West Design & Test Symposium, 2018

2017
Improving of a Circuit Checkability and Trustworthiness of Data Processing Results in LUT-based FPGA Components of Safety-Related Systems.
Proceedings of the 13th International Conference on ICT in Education, 2017

Models and methods checking mantissas by inequalities for on-line testing of digital circuits in critical applications.
Proceedings of the 2017 IEEE East-West Design & Test Symposium, 2017

2016
Use of Natural LUT Redundancy to Improve Trustworthiness of FPGA Design.
Proceedings of the 12th International Conference on ICT in Education, 2016

2015
Features of Hidden Fault Detection in Pipeline Digital Components of Safety-Related Systems.
Proceedings of the 11th International Conference on ICT in Education, 2015

2011
Checkability of the digital components in safety-critical systems: Problems and solutions.
Proceedings of the 9th East-West Design & Test Symposium, 2011


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