Mubin Ul Haque

According to our database, Mubin Ul Haque authored at least 11 papers between 2016 and 2023.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of five.

2023

A Study on Early & Non-Intrusive Security Assessment for Container Images.

Mubin Ul Haque, Muhammad Ali Babar

Proceedings of the 18th International Conference on Evaluation of Novel Approaches to Software Engineering, 2023

2022

"I think this is the most disruptive technology": Exploring Sentiments of ChatGPT Early Adopters using Twitter Data.

Mubin Ul Haque, Isuru Dharmadasa, Zarrin Tasnim Sworna, Roshan Namal Rajapakse, Hussain Ahmad

CoRR, 2022

A Cost-Efficient Look-Up Table Based Binary Coded Decimal Adder Design.

Zarrin Tasnim Sworna, Mubin Ul Haque, Hafiz Md. Hasan Babu, Lafifa Jamal

CoRR, 2022

KGSecConfig: A Knowledge Graph Based Approach for Secured Container Orchestrator Configuration.

Mubin Ul Haque, M. Mehdi Kholoosi, Muhammad Ali Babar

Proceedings of the IEEE International Conference on Software Analysis, 2022

Well Begun is Half Done: An Empirical Study of Exploitability & Impact of Base-Image Vulnerabilities.

Mubin Ul Haque, Muhammad Ali Babar

Proceedings of the IEEE International Conference on Software Analysis, 2022

2020

Challenges in Docker Development: A Large-scale Study Using Stack Overflow.

Mubin Ul Haque, Leonardo Horn Iwaya, Muhammad Ali Babar

Proceedings of the ESEM '20: ACM / IEEE International Symposium on Empirical Software Engineering and Measurement, 2020

2018

A Fast FPGA-Based BCD Adder.

Mubin Ul Haque, Zarrin Tasnim Sworna, Hafiz Md. Hasan Babu, Ashis Kumer Biswas

Circuits Syst. Signal Process., 2018

2017

An Efficient Design of an FPGA-Based Multiplier Using LUT Merging Theorem.

Zarrin Tasnim Sworna, Mubin Ul Haque, Hafiz Md. Hasan Babu, Lafifa Jamal, Ashis Kumer Biswas

Proceedings of the 2017 IEEE Computer Society Annual Symposium on VLSI, 2017

2016

Low-power and area efficient binary coded decimal adder design using a look up table-based field programmable gate array.

Zarrin Tasnim Sworna, Mubin Ul Haque, Nazma Tara, Hafiz Md. Hasan Babu, Ashis Kumer Biswas

IET Circuits Devices Syst., 2016

An Improved Design of a Reversible Fault Tolerant LUT-based FPGA.

Mubin Ul Haque, Zarrin Tasnim Sworna, Hafiz Md. Hasan Babu

Proceedings of the 29th International Conference on VLSI Design and 15th International Conference on Embedded Systems, 2016

A LUT-based matrix multiplication using neural networks.

Zarrin Tasnim Sworna, Mubin Ul Haque, Hafiz Md. Hasan Babu

Proceedings of the IEEE International Symposium on Circuits and Systems, 2016