Lafifa Jamal

Orcid: 0000-0002-3314-7514

According to our database1, Lafifa Jamal authored at least 25 papers between 2010 and 2023.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

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Online presence:

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Bibliography

2023
[email protected]: Third Workshop on Gender Equality, Diversity, and Inclusion in Software Engineering.
ACM SIGSOFT Softw. Eng. Notes, January, 2023

STPT: Spatio-Temporal Polychromatic Trajectory Based Elderly Exercise Evaluation System.
IEEE Access, 2023

2022
A Novel IOT-Based Medicine Consumption System for Elders.
SN Comput. Sci., 2022

A Cost-Efficient Look-Up Table Based Binary Coded Decimal Adder Design.
CoRR, 2022

2021
Robotics and artificial intelligence in healthcare during COVID-19 pandemic: A systematic review.
Robotics Auton. Syst., 2021

2020
An IoT Based Smart System to Recommend Suitable Environment.
Proceedings of the ICRAI 2020: 6th International Conference on Robotics and Artificial Intelligence, 2020

2018
Towards Designing Optimized Low Power Reversible Demultiplexer for Emerging Nanocircuits.
Proceedings of the 31st IEEE International System-on-Chip Conference, 2018

2017
Power efficient optimum design of the Reversible Plessey Logic Block of a field-programmable gate array.
Sustain. Comput. Informatics Syst., 2017

An Efficient Design of an FPGA-Based Multiplier Using LUT Merging Theorem.
Proceedings of the 2017 IEEE Computer Society Annual Symposium on VLSI, 2017

Area and Delay Efficient Design of a Quantum Bit String Comparator.
Proceedings of the 2017 IEEE Computer Society Annual Symposium on VLSI, 2017

2016
Design of a Compact Reversible Read-Only-Memory with MOS Transistors.
CoRR, 2016

Design of an optimized reversible bidirectional barrel shifter.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2016

An efficient design technique of a quantum divider circuit.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2016

2015
Design and Implementation of a Reversible Central Processing Unit.
Proceedings of the 2015 IEEE Computer Society Annual Symposium on VLSI, 2015

2014
Approach to design a compact reversible low power binary comparator.
IET Comput. Digit. Tech., 2014

2013
An efficient approach to design a reversible control unit of a processor.
Sustain. Comput. Informatics Syst., 2013

Design of a compact reversible fault tolerant field programmable gate array: A novel approach in reversible logic synthesis.
Microelectron. J., 2013

Design of a Fault Tolerant Reversible Compact Unidirectional Barrel Shifter.
Proceedings of the 26th International Conference on VLSI Design and 12th International Conference on Embedded Systems, 2013

An optimal design of a fault tolerant reversible multiplier.
Proceedings of the 2013 IEEE International SOC Conference, Erlangen, Germany, 2013

An efficient approach for designing a reversible fault tolerant n-bit carry look-ahead adder.
Proceedings of the 2013 IEEE International SOC Conference, Erlangen, Germany, 2013

Efficient approaches to design a reversible floating point divider.
Proceedings of the 2013 IEEE International Symposium on Circuits and Systems (ISCAS2013), 2013

2012
On the Compact Designs of Low Power Reversible Decoders and Sequential Circuits.
Proceedings of the Progress in VLSI Design and Test - 16th International Symposium, 2012

An efficient approach for designing and minimizing reversible programmable logic arrays.
Proceedings of the Great Lakes Symposium on VLSI 2012, 2012

2011
Realization of Reversible Logic in DNA Computing.
Proceedings of the 11th IEEE International Conference on Bioinformatics and Bioengineering, 2011

2010
Building Toffoli Network for Reversible Logic Synthesis Based on Swapping Bit Strings
CoRR, 2010


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