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Mummaneni Kavicharan

Orcid: 0000-0003-1074-3564

Affiliations:
  • National Institute of Technology Warangal, India


According to our database1, Mummaneni Kavicharan authored at least 4 papers between 2013 and 2016.

Collaborative distances:
  • Dijkstra number2 of six.
  • Erdős number3 of five.

Timeline

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Online presence:

On csauthors.net:

Bibliography

2016
Modeling and Analysis of On-Chip Single and H-tree Distributed RLC Interconnects.
[BibTeX]
[DOI]
Mummaneni Kavicharan
,
Nukala Suryanarayana Murthy
,
N. Bheema Rao
,
Addanki Prathima
Circuits Syst. Signal Process., 2016

2015
A Survey on FDTD-Based Interconnect Modeling.
[BibTeX]
[DOI]
Nukala Suryanarayana Murthy
,
Mummaneni Kavicharan
J. Circuits Syst. Comput., 2015

2014
Efficient delay and Crosstalk estimation Models for Current-mode High Speed interconnects under Ramp input.
[BibTeX]
[DOI]
Mummaneni Kavicharan
,
Nukala Suryanarayana Murthy
,
N. Bheema Rao
J. Circuits Syst. Comput., 2014

2013
An efficient delay estimation model for high speed VLSI interconnects.
[BibTeX]
[DOI]
Mummaneni Kavicharan
,
Nukala Suryanarayana Murthy
,
N. Bheema Rao
Proceedings of the International Conference on Advances in Computing, 2013


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