N. Bheema Rao

According to our database, N. Bheema Rao authored at least 6 papers between 2013 and 2022.

Collaborative distances:

• Dijkstra number of six.
• Erdős number of five.

2022

Stacked Multi-layer Zig-Zag On-chip Inductor.

Manchala Naveen, N. Bheema Rao

Proceedings of the IEEE International Symposium on Smart Electronic Systems, 2022

2020

A FinFET based 2^nd-Order Fully Differential Passive Sigma Delta Modulator for Low Power ADC.

K. Sarangam, N. Bheema Rao

Proceedings of the 11th International Conference on Computing, 2020

2016

Modeling and Analysis of On-Chip Single and H-tree Distributed RLC Interconnects.

Mummaneni Kavicharan, Nukala Suryanarayana Murthy, N. Bheema Rao, Addanki Prathima

Circuits Syst. Signal Process., 2016

2014

Power gating Technique using FinFET for Minimization of sub-Threshold Leakage Current.

K. Keerti Kumar, N. Bheema Rao

J. Circuits Syst. Comput., 2014

Efficient delay and Crosstalk estimation Models for Current-mode High Speed interconnects under Ramp input.

Mummaneni Kavicharan, Nukala Suryanarayana Murthy, N. Bheema Rao

J. Circuits Syst. Comput., 2014

2013

An efficient delay estimation model for high speed VLSI interconnects.

Mummaneni Kavicharan, Nukala Suryanarayana Murthy, N. Bheema Rao

Proceedings of the International Conference on Advances in Computing, 2013