Munish Malik

According to our database, Munish Malik authored at least 3 papers between 2017 and 2025.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of six.

2025

Analyzing the Effectiveness of Various NMOS Layouts for Total Ionizing Dose Hardening in 180nm CMOS.

Munish Malik, Neelam Rup Prakash, Ajay Kumar, Jasbir Kaur, Amit Singh, Kavita Monga

J. Electron. Test., June, 2025

2023

Comparative analysis of radiation tolerant analog circuit layout in 180 nm CMOS technology for space application.

Munish Malik, Neelam Rup Prakash, Ajay Kumar

Microelectron. J., 2023

2017

Design & Development of High Speed LVDS Receiver with Cold-Spare Feature in SCL's 0.18 µm CMOS Process.

Munish Malik, Ajay Kumar, H. S. Jatana

Proceedings of the VLSI Design and Test - 21st International Symposium, 2017