H. S. Jatana

According to our database, H. S. Jatana authored at least 3 papers between 2017 and 2021.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of five.

2021

Total ionizing dose hardness analysis of transistors in commercial 180 nm CMOS technology.

Mukesh Kumar, Jagpal Singh Ubhi, Sanjeev Basra, Anuj Chawla, H. S. Jatana

Microelectron. J., 2021

2019

A Physics-Based Variability-Aware Methodology to Estimate Critical Charge for Near-Threshold Voltage Latches.

Chaudhry Indra Kumar, Ishant Bhatia, Arvind Kumar Sharma, Deep Sehgal, H. S. Jatana, Anand Bulusu

IEEE Trans. Very Large Scale Integr. Syst., 2019

2017

Design & Development of High Speed LVDS Receiver with Cold-Spare Feature in SCL's 0.18 µm CMOS Process.

Munish Malik, Ajay Kumar, H. S. Jatana

Proceedings of the VLSI Design and Test - 21st International Symposium, 2017