Myeongho Han

According to our database, Myeongho Han authored at least 5 papers between 2024 and 2026.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of five.

2026

A Command-Aware Hybrid LDO With Ultra-Small Voltage Droop and Fast Settling Time for Power-Supply-Induced Jitter Mitigation in HBM Interfaces.

Jaeho Kim, Myeongho Han, Hyunjun Song, Jooeun Bang, Younghyun Lim, Jaehyouk Choi

IEEE J. Solid State Circuits, January, 2026

A Comprehensive Power-Supply-Induced Jitter Mitigation Scheme for HBM Interfaces Using a Strobe-Triggered Digital LDO and Local Replica Regulators Achieving 10.7mV Voltage Droop and 1.4ns Settling Time.

Myeongho Han, Jaeho Kim, Hyunjun Song, Jaehyouk Choi

Proceedings of the IEEE Custom Integrated Circuits Conference, 2026

2025

A Low-Reference-Spur and Low-Jitter D-Band PLL With Complementary Power-Gating Injection-Locked Frequency-Multiplier-Based Phase Detector.

Jaeho Kim, Jooeun Bang, Seohee Jung, Myeongho Han, Jaehyouk Choi

IEEE Solid State Circuits Lett., 2025

8.5 A Command-Aware Hybrid LDO for Advanced HBM Interfaces with 150μA Quiescent Current and 20pF On-Chip Capacitor Achieving Sub-10mV Voltage Droop in 400ps Settling Time.

Jaeho Kim, Myeongho Han, Jooeun Bang, Younghyun Lim, Jaehyouk Choi

Proceedings of the IEEE International Solid-State Circuits Conference, 2025

2024

A -51dBc-Reference-Spur and 66fsrms-Jitter D-Band PLL with Complementary Power-Gating Injection-Locked Frequency-Multiplier-Based Phase Detector.

Jaeho Kim, Jooeun Bang, Seohee Jung, Myeongho Han, Jaehyouk Choi

Proceedings of the IEEE Asian Solid-State Circuits Conference, 2024