N. Verrascina

According to our database¹, N. Verrascina authored at least 2 papers between 2016 and 2019.

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2019

Clock-less 8-bit SAR-ADC with delay-line based digital control circuit.

[BibT_eX]

[DOI]

Microelectron. J., 2019

2016

An ULP and very efficient adaptively biased LDO regulator for harvesting application.

[BibT_eX]

[DOI]

Proceedings of the 14th IEEE International New Circuits and Systems Conference, 2016