Nadav Rotem

According to our database, Nadav Rotem authored at least 16 papers between 2008 and 2021.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2021

Profile Guided Optimization without Profiles: A Machine Learning Approach.

Nadav Rotem, Chris Cummins

CoRR, 2021

2020

Warrior1: A Performance Sanitizer for C++.

Nadav Rotem, Lee Howes, David Goldblatt

CoRR, 2020

2018

Deep Learning Inference in Facebook Data Centers: Characterization, Performance Optimizations and Hardware Implications.

Jongsoo Park, Maxim Naumov, Protonu Basu, Summer Deng, Aravind Kalaiah, Daya Shanker Khudia, James Law, Parth Malani, Andrey Malevich, Nadathur Satish, Juan Miguel Pino, Martin Schatz, Alexander Sidorov, Viswanath Sivakumar, Andrew Tulloch, Xiaodong Wang, Yiming Wu, Hector Yuen, Utku Diril, Dmytro Dzhulgakov, Kim M. Hazelwood, Bill Jia, Yangqing Jia, Lin Qiao, Vijay Rao, Nadav Rotem, Sungjoo Yoo, Mikhail Smelyanskiy

CoRR, 2018

Glow: Graph Lowering Compiler Techniques for Neural Networks.

Nadav Rotem, Jordan Fix, Saleem Abdulrasool, Summer Deng, Roman Dzhabarov, James Hegeman, Roman Levenstein, Bert Maher, Nadathur Satish, Jakob Olesen, Jongsoo Park, Artem Rakhov, Misha Smelyanskiy

CoRR, 2018

2014

Block Unification IF-conversion for High Performance Architectures.

Nadav Rotem, Yosi Ben-Asher

IEEE Comput. Archit. Lett., 2014

2013

Optimizing Wait States in the Synthesis of Memory References with Unpredictable Latencies.

Yosi Ben-Asher, Ron Meldiner, Nadav Rotem

ACM Trans. Reconfigurable Technol. Syst., 2013

The benefits of using variable-length pipelined operations in high-level synthesis.

Yosi Ben-Asher, Nadav Rotem

ACM Trans. Embed. Comput. Syst., 2013

Using memory profile analysis for automatic synthesis of pointers code.

Yosi Ben-Asher, Nadav Rotem

ACM Trans. Embed. Comput. Syst., 2013

Hybrid type legalization for a sparse SIMD instruction set.

Yosi Ben-Asher, Nadav Rotem

ACM Trans. Archit. Code Optim., 2013

2011

Combining static and dynamic array detection for binary synthesis with multiple memory ports.

Nadav Rotem, Yosi Ben-Asher

Des. Autom. Embed. Syst., 2011

2010

Reducing Memory Constraints in Modulo Scheduling Synthesis for FPGAs.

Yosi Ben-Asher, Danny Meisler, Nadav Rotem

ACM Trans. Reconfigurable Technol. Syst., 2010

Finding the best compromise in compiling compound loops to Verilog.

Yosi Ben-Asher, Nadav Rotem, Eddie Shochat

J. Syst. Archit., 2010

Automatic memory partitioning: increasing memory parallelism via data structure partitioning.

Yosi Ben-Asher, Nadav Rotem

Proceedings of the 8th International Conference on Hardware/Software Codesign and System Synthesis, 2010

2009

The effect of unrolling and inlining for Python bytecode optimizations.

Yosi Ben-Asher, Nadav Rotem

Proceedings of of SYSTOR 2009: The Israeli Experimental Systems Conference 2009, 2009

Binary Synthesis with multiple memory banks targeting array references.

Yosi Ben-Asher, Nadav Rotem

Proceedings of the 19th International Conference on Field Programmable Logic and Applications, 2009

2008

Synthesis for variable pipelined function units.

Yosi Ben-Asher, Nadav Rotem

Proceedings of the 2008 IEEE International Symposium on System-on-Chip, 2008