Yosi Ben-Asher

According to our database1, Yosi Ben-Asher authored at least 108 papers between 1984 and 2019.

Collaborative distances:

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Other 

Links

Homepages:

On csauthors.net:

Bibliography

2019
Efficient Conversion of Boolean Circuits to Nondeterministic Branching Programs.
Proceedings of the IEEE International Parallel and Distributed Processing Symposium Workshops, 2019

Evaluation of Circuits on the Reconfigurable Mesh.
Proceedings of the IEEE International Parallel and Distributed Processing Symposium Workshops, 2019

2018
Software Static Energy Modeling for Modern Processors.
International Journal of Parallel Programming, 2018

A first-order approximation of microarchitecture energy-efficiency.
Proceedings of the 18th International Conference on Embedded Computer Systems: Architectures, 2018

An FPGA Scalable Parallel Viterbi Decoder.
Proceedings of the 12th IEEE International Symposium on Embedded Multicore/Many-core Systems-on-Chip, 2018

Unifying Wire and Time Scheduling for Highlevel Synthesis.
Proceedings of the 12th IEEE International Symposium on Embedded Multicore/Many-core Systems-on-Chip, 2018

2017
A Study of Conflicting Pairs of Compiler Optimizations.
Proceedings of the 11th IEEE International Symposium on Embedded Multicore/Many-core Systems-on-Chip, 2017

Combining Boolean Gates and Branching Programs in One Model can Lead to Faster Circuits.
Proceedings of the 2017 IEEE International Parallel and Distributed Processing Symposium Workshops, 2017

2016
Fine-Grain Power Breakdown of Modern Out-of-Order Cores and Its Implications on Skylake-Based Systems.
TACO, 2016

Adaptive Booth Algorithm for Three-integers Multiplication for Reconfigurable Mesh.
Journal of Interconnection Networks, 2016

2015
DOEE: dynamic optimization framework for better energy efficiency.
Proceedings of the Symposium on High Performance Computing, 2015

A study of manycore shared memory architecture as a way to build SOC applications.
Proceedings of the Symposium on High Performance Computing, 2015

Generating ASIPs with reduced number of connections to the register-file.
Proceedings of the 2015 International Conference on Embedded Computer Systems: Architectures, 2015

Streamlining Whole Function Vectorization in C Using Higher Order Vector Semantics.
Proceedings of the 2015 IEEE International Parallel and Distributed Processing Symposium Workshop, 2015

2014
Compiler-Directed Power Management for Superscalars.
TACO, 2014

Block Unification IF-conversion for High Performance Architectures.
Computer Architecture Letters, 2014

Parallelization hints via code skeletonization.
Proceedings of the ACM SIGPLAN Symposium on Principles and Practice of Parallel Programming, 2014

Adaptive Booth Algorithm for Three-Integers Multiplication for Reconfigurable Mesh.
Proceedings of the 2014 IEEE International Parallel & Distributed Processing Symposium Workshops, 2014

Deep-dive analysis of the data analytics workload in CloudSuite.
Proceedings of the 2014 IEEE International Symposium on Workload Characterization, 2014

1K manycore FPGA shared memory architecture for SOC (abstract only).
Proceedings of the 2014 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, 2014

Using Multi-op Instructions as a Way to Generate ASIPs with Optimized Pipeline Structure.
Proceedings of the 22nd IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, 2014

2013
The benefits of using variable-length pipelined operations in high-level synthesis.
ACM Trans. Embedded Comput. Syst., 2013

Using memory profile analysis for automatic synthesis of pointers code.
ACM Trans. Embedded Comput. Syst., 2013

Hybrid type legalization for a sparse SIMD instruction set.
TACO, 2013

2012
Combining Height Reduction and Scheduling for VLIW Machines Enhanced with Three-Argument Arithmetic Operations.
International Journal of Parallel Programming, 2012

Refactoring techniques for aggressive object inlining in Java applications.
Autom. Softw. Eng., 2012

Fast Evaluation of Boolean Circuits Based on Two-Players Game and Optical Connectivity Circuits.
Proceedings of the 41st International Conference on Parallel Processing, 2012

Multicore Programming Using the ParC Language.
Undergraduate Topics in Computer Science, Springer, ISBN: 978-1-4471-2163-3, 2012

2011
Auctions by price and distance via cellular phones.
Electronic Commerce Research and Applications, 2011

Combining static and dynamic array detection for binary synthesis with multiple memory ports.
Design Autom. for Emb. Sys., 2011

Dynamic Multipath Allocation in Ad Hoc Networks.
Comput. J., 2011

Optimizing wait-states in the synthesis of memory references with unpredictable latencies.
Proceedings of the 2011 International Conference on Embedded Computer Systems: Architectures, 2011

2010
Scalability Issues in Ad-Hoc Networks: Metrical Routing Versus Table-Driven Routing.
Wireless Personal Communications, 2010

Reducing Memory Constraints in Modulo Scheduling Synthesis for FPGAs.
TRETS, 2010

Finding the best compromise in compiling compound loops to Verilog.
Journal of Systems Architecture - Embedded Systems Design, 2010

Computing the correct Increment of Induction Pointers with application to loop unrolling.
Journal of Systems Architecture - Embedded Systems Design, 2010

HparC: a mixed nested shared memory and message passing programming style intended for grid.
Proceedings of of SYSTOR 2010: The 3rd Annual Haifa Experimental Systems Conference, 2010

Automatic memory partitioning: increasing memory parallelism via data structure partitioning.
Proceedings of the 8th International Conference on Hardware/Software Codesign and System Synthesis, 2010

2009
The effect of unrolling and inlining for Python bytecode optimizations.
Proceedings of of SYSTOR 2009: The Israeli Experimental Systems Conference 2009, 2009

Binary Synthesis with multiple memory banks targeting array references.
Proceedings of the 19th International Conference on Field Programmable Logic and Applications, 2009

2008
Distributed Decision and Control for Cooperative UAVs Using Ad Hoc Communication.
IEEE Trans. Contr. Sys. Techn., 2008

Hierarchical Task Assignment and Communication Algorithms for Unmanned Aerial Vehicle Flocks.
JACIC, 2008

Finding the Best Compromise in Compiling Compound Loops to Verilog.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2008

Aggressive Function Inlining: Preventing Loop Blockings in the Instruction Cache.
Proceedings of the High Performance Embedded Architectures and Compilers, 2008

Extending Booth algorithm to multiplications of three numbers on FPGAs.
Proceedings of the 2008 International Conference on Field-Programmable Technology, 2008

Adaptive Retrieval of Semi-structured Data.
Proceedings of the Adaptive Hypermedia and Adaptive Web-Based Systems, 2008

2007
IFAS: Interactive flexible ad hoc simulator.
Simulation Modelling Practice and Theory, 2007

Source Level Merging of Independent Programs.
Proceedings of the 16th International Conference on Parallel Architectures and Compilation Techniques (PACT 2007), 2007

2006
Semantic Data Management in Peer-to-Peer E-Commerce Applications.
, 2006

Ad-Hoc Routing Using Virtual Coordinates Based on Rooted Trees.
Proceedings of the IEEE International Conference on Sensor Networks, 2006

Management of unspecified semi-structured data in multi-agent environment.
Proceedings of the 2006 ACM Symposium on Applied Computing (SAC), 2006

Metrical Routing using Ad-Hoc Networks in Hierarchical Environment.
Proceedings of the ITRE 2006, 2006

Producing scheduling that causes concurrent programs to fail.
Proceedings of the 4th Workshop on Parallel and Distributed Systems: Testing, 2006

Noise Makers Need to Know Where to be Silent - Producing Schedules That Find Bugs.
Proceedings of the Leveraging Applications of Formal Methods, 2006

Towards a Source Level Compiler: Source Level Modulo Scheduling.
Proceedings of the 2006 International Conference on Parallel Processing Workshops (ICPP Workshops 2006), 2006

Towards a Source Level Compiler: Source Level Modulo Scheduling.
Proceedings of the Program Analysis and Compilation, 2006

2005
Using J2EE/NET Clusters for Parallel Computations of Join Queries in Distributed Databases.
JDIM, 2005

Compact Representations of Search in Complex Domains.
IGTR, 2005

Compact Representations of Search in Complex Domains.
IGTR, 2005

Optimal Algorithmic Debugging and Reduced Coverage Using Search in Structured Domains.
Proceedings of the Hardware and Software Verification and Testing, 2005

2004
Using a J2EE Cluster for Parallel Computation of Join Queries in Distributed Databases.
Proceedings of the 3rd International Symposium on Parallel and Distributed Computing (ISPDC 2004), 2004

Overlapping Memory Operations with Circuit Evaluation in Reconfigurable Computing.
Proceedings of the 18th International Parallel and Distributed Processing Symposium (IPDPS 2004), 2004

2003
Heuristics for Finding Concurrent Bug.
Proceedings of the 17th International Parallel and Distributed Processing Symposium (IPDPS 2003), 2003

2002
Basic Algorithms for the Asynchronous Reconfigurable Mesh.
VLSI Design, 2002

The parallel client-server paradigm.
Parallel Computing, 2002

Communication - Processor Tradeoffs in a Limited Resources PRAM.
Algorithmica, 2002

Basic Algorithms for the Asynchronous Reconfigurable Mes.
Proceedings of the 16th International Parallel and Distributed Processing Symposium (IPDPS 2002), 2002

2001
Parallel Solutions of Simple Indexed Recurrence Equations.
IEEE Trans. Parallel Distrib. Syst., 2001

Distributed Routing of Ads and Bids through Random Walks in the IDOS System.
J. Parallel Distrib. Comput., 2001

Y-Invalidate: A New Protocol for Implementing Weak Consistency in DSM Systems.
International Journal of Parallel Programming, 2001

1999
Optimal Search in Trees.
SIAM J. Comput., 1999

Efficient Parallel Solutions of Linear Algebraic Circuits.
Proceedings of the Eleventh Annual ACM Symposium on Parallel Algorithms and Architectures, 1999

Communication-Processor Tradeoffs in Limited Resources PRAM.
Proceedings of the Eleventh Annual ACM Symposium on Parallel Algorithms and Architectures, 1999

1998
Parallel Solutions of Simple Index Recurrence Equations.
Proceedings of the Euro-Par '98 Parallel Processing, 1998

1997
Optical Routing in Meshes Using the Duplication Model.
J. Parallel Distrib. Comput., 1997

Geometric Approach for Optimal Routing on a Mesh with Buses.
J. Comput. Syst. Sci., 1997

Optimal Search in Trees: Extended Abstract + Appendix.
Proceedings of the Eighth Annual ACM-SIAM Symposium on Discrete Algorithms, 1997

Parallel Solutions of Indexed Recurrence Equations.
Proceedings of the 11th International Parallel Processing Symposium (IPPS '97), 1997

Single step undirected reconfigurable networks.
Proceedings of the Fourth International on High-Performance Computing, 1997

Basic Results in Automatic Transformations of Shared Memory Parallel Programs into Sequential Programs.
Proceedings of the Advances in Computing Science, 1997

1996
ParC - An Extension of C for Shared Memory Parallel Processing.
Softw., Pract. Exper., 1996

Time-Size Tradeoffs for Reconfigurable Meshes.
Parallel Processing Letters, 1996

Low Crosstalk Address Encodings for Optical Message Switching Systems.
Parallel Processing Letters, 1996

On the usage of simulators to detect inefficiency of parallel programs caused by "bad" schedulings: The Simparc approach.
Journal of Systems and Software, 1996

Geometric Approach for Optimal Routing on Mesh with Buses
Electronic Colloquium on Computational Complexity (ECCC), 1996

Optimal Search in Trees
Electronic Colloquium on Computational Complexity (ECCC), 1996

1995
The Complexity of Reconfiguring Network Models
Inf. Comput., August, 1995

The Cartesian Product Problem and Implementing Production Systems on Reconfigurable Meshes.
Parallel Processing Letters, 1995

Decision Trees with Boolean Threshold Queries.
J. Comput. Syst. Sci., 1995

The Complexity of Data Reduction on a Reconfigurable Linear Array.
J. Algorithms, 1995

2DT-FP: A parallel functional programming language on two-dimensional data.
International Journal of Parallel Programming, 1995

Load Balancing: a Programmer's Approach or the Impact of Task-Length Parameters on the Load Balancing Performance of Parallel Programs.
International Journal of High Speed Computing, 1995

Geometric approach for optimal routing on mesh with buses.
Proceedings of the Seventh IEEE Symposium on Parallel and Distributed Processing, 1995

Decision Trees with AND, OR Queries.
Proceedings of the Tenth Annual Structure in Complexity Theory Conference, 1995

1994
Using true concurrency to model execution of parallel programs.
International Journal of Parallel Programming, 1994

Implementing 2DT on a Multiprocessor.
Proceedings of the Compiler Construction, 5th International Conference, 1994

1993
2DT-FP: An FP Based Programming Language for Efficient Parallel Programming of Multiprocessor Networks.
Proceedings of the PARLE '93, 1993

Low Crosstalk Address Encodings for Optical Message Switching Systems..
Proceedings of the Seventh International Parallel Processing Symposium, 1993

Efficient Self Simulation Algorithms for Reconfigurable Arrays.
Proceedings of the Algorithms - ESA '93, First Annual European Symposium, Bad Honnef, Germany, September 30, 1993

1992
2-D SIMD Algorithms for Perfect Shuffle Networks.
J. Parallel Distrib. Comput., 1992

The Complexity of Reconfiguring Network Models.
Proceedings of the Theory of Computing and Systems, 1992

The Bus-Usage Method for the Analysis of Reconfiguring Networks Algorithms.
Proceedings of the 6th International Parallel Processing Symposium, 1992

The Impact of Task-Length Parameters on the Performance of the Random Load-Balancing Algorithm.
Proceedings of the 6th International Parallel Processing Symposium, 1992

1991
Ranking on Reconfigurable Networks.
Parallel Processing Letters, 1991

The POwer of Reconfiguration.
Proceedings of the Automata, Languages and Programming, 18th International Colloquium, 1991

1990
Algorithms and optic implementation for reconfigurable networks.
Proceedings of the Next Decade in Information Technology: Proceedings of the 5th Jerusalem Conference on Information Technology 1990, 1990

1989
2-D SIMD Algorithms in the Perfect Shuffle Networks.
Proceedings of the 16th Annual International Symposium on Computer Architecture. Jerusalem, 1989

1984
HUHU: The Hebrew University Hebrew Understander.
Comput. Lang., 1984


  Loading...