Nagaraja Revanna

According to our database, Nagaraja Revanna authored at least 4 papers between 2016 and 2018.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2018

Memristor Adder Design.

Nagaraja Revanna, Earl E. Swartzlander Jr.

Proceedings of the IEEE 61st International Midwest Symposium on Circuits and Systems, 2018

2017

The future of computing - Arithmetic circuits implemented with memristors.

Nagaraja Revanna, Lauren Guckert, Earl E. Swartzlander Jr.

Proceedings of the 51st Asilomar Conference on Signals, Systems, and Computers, 2017

2016

Arithmetic circuit design with memristor based high fan-out logic gates.

Nagaraja Revanna, Earl E. Swartzlander Jr.

Proceedings of the 7th IEEE Annual Ubiquitous Computing, 2016

Memristor based adder circuit design.

Nagaraja Revanna, Earl E. Swartzlander Jr.

Proceedings of the 50th Asilomar Conference on Signals, Systems and Computers, 2016