Earl E. Swartzlander Jr.
According to our database^{1},
Earl E. Swartzlander Jr.
authored at least 204 papers
between 1973 and 2019.
Collaborative distances:
Collaborative distances:
Awards
IEEE Fellow
IEEE Fellow 1988, "For contributions to VLSI design of specialized signal processors.".
Timeline
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Homepages:

at orcid.org
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Bibliography
2019
Design and Analysis of Approximate Redundant Binary Multipliers.
IEEE Trans. Computers, 2019
2018
Designs of Approximate FloatingPoint Multipliers with Variable Accuracy for ErrorTolerant Applications.
Signal Processing Systems, 2018
Design of HighSpeed WideWord Hybrid ParallelPrefix/CarrySelect and Skip Adders.
Signal Processing Systems, 2018
Data Compression Device Based on Modified LZ4 Algorithm.
IEEE Trans. Consumer Electronics, 2018
MemristorBased Computing.
IEEE Micro, 2018
Memristor Adder Design.
Proceedings of the IEEE 61st International Midwest Symposium on Circuits and Systems, 2018
2017
Guest Editorial: Introduction to the Special Issue on Emerging Technologies and Designs for ApplicationSpecific Computing.
IEEE Trans. Emerging Topics Comput., 2017
MAD Gates  Memristor Logic Design Using Driver Circuitry.
IEEE Trans. on Circuits and Systems, 2017
Optimized MemristorBased Multipliers.
IEEE Trans. on Circuits and Systems, 2017
High Performance Parallel Decimal Multipliers Using Hybrid BCD Codes.
IEEE Trans. Computers, 2017
Dadda Multiplier designs using memristors.
Proceedings of the 2017 IEEE International Conference on IC Design and Technology, 2017
The future of computing  Arithmetic circuits implemented with memristors.
Proceedings of the 51st Asilomar Conference on Signals, Systems, and Computers, 2017
Parallel GF(2^{n}) multipliers.
Proceedings of the 51st Asilomar Conference on Signals, Systems, and Computers, 2017
2016
A Fused FloatingPoint FourTerm Dot Product Unit.
IEEE Trans. on Circuits and Systems, 2016
A Modified Partial Product Generator for Redundant Binary Multipliers.
IEEE Trans. Computers, 2016
Arithmetic circuit design with memristor based high fanout logic gates.
Proceedings of the IEEE 7th Annual Ubiquitous Computing, 2016
Memristor based adder circuit design.
Proceedings of the 50th Asilomar Conference on Signals, Systems and Computers, 2016
Optimized memristorbased ripple carry adders.
Proceedings of the 50th Asilomar Conference on Signals, Systems and Computers, 2016
2015
Design of 3D quantumdot cellular automata adders.
IEICE Electronic Express, 2015
LowCost Duplicate Multiplication.
Proceedings of the 22nd IEEE Symposium on Computer Arithmetic, 2015
Exploiting asymmetry in Boothencoded multipliers for reduced energy multiplication.
Proceedings of the 49th Asilomar Conference on Signals, Systems and Computers, 2015
Extreme multicore, multinetwork Java DataFlow Machine (JavaFlow).
Proceedings of the 49th Asilomar Conference on Signals, Systems and Computers, 2015
2014
Security Issues in QCA Circuit Design  Power Analysis Attacks.
Proceedings of the FieldCoupled Nanocomputing  Paradigms, Progress, and Perspectives, 2014
A Fused FloatingPoint ThreeTerm Adder.
IEEE Trans. on Circuits and Systems, 2014
Design of Goldschmidt Dividers with QuantumDot Cellular Automata.
IEEE Trans. Computers, 2014
Memristor based adders.
Proceedings of the 48th Asilomar Conference on Signals, Systems and Computers, 2014
Improved nonrestoring square root algorithm with dual path calculation.
Proceedings of the 48th Asilomar Conference on Signals, Systems and Computers, 2014
HighSpeed Computer Arithmetic.
Proceedings of the Computing Handbook, 2014
2013
StructureAware Placement Techniques for Designs With Datapaths.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2013
QCA Systolic Array Design.
IEEE Trans. Computers, 2013
STARS: Electronic Calculators: Desktop to Pocket.
Proceedings of the IEEE, 2013
Power analysis attack of QCA circuits: A case study of the Serpent cipher.
Proceedings of the 2013 IEEE International Symposium on Circuits and Systems (ISCAS2013), 2013
The optimum Booth radix for low power integer multipliers.
Proceedings of the 8th International Design and Test Symposium, 2013
Fused floatingpoint twoterm sumofsquares unit.
Proceedings of the 24th International Conference on ApplicationSpecific Systems, 2013
Truncated Logarithmic Approximation.
Proceedings of the 21st IEEE Symposium on Computer Arithmetic, 2013
Improved Architectures for a FloatingPoint Fused Dot Product Unit.
Proceedings of the 21st IEEE Symposium on Computer Arithmetic, 2013
On separable error detection for addition.
Proceedings of the 2013 Asilomar Conference on Signals, 2013
Implementation of a high speed multiplier using carry lookahead adders.
Proceedings of the 2013 Asilomar Conference on Signals, 2013
2012
Improved Architectures for a Fused FloatingPoint AddSubtract Unit.
IEEE Trans. on Circuits and Systems, 2012
FFT Implementation with Fused FloatingPoint Operations.
IEEE Trans. Computers, 2012
A new hierarchical packet classification algorithm.
Computer Networks, 2012
Keep it straight: teaching placement how to better handle designs with datapaths.
Proceedings of the International Symposium on Physical Design, 2012
Costefficient decimal adder design in Quantumdot cellular automata.
Proceedings of the 2012 IEEE International Symposium on Circuits and Systems, 2012
Long Residue Checking for Adders.
Proceedings of the 23rd IEEE International Conference on ApplicationSpecific Systems, 2012
Truncated error correction for flexible approximate multiplication.
Proceedings of the Conference Record of the Forty Sixth Asilomar Conference on Signals, 2012
A lowpower dualpath floatingpoint fused addsubtract unit.
Proceedings of the Conference Record of the Forty Sixth Asilomar Conference on Signals, 2012
A review of QCA adders and metrics.
Proceedings of the Conference Record of the Forty Sixth Asilomar Conference on Signals, 2012
Modified nonrestoring division algorithm with improved delay profile and error correction.
Proceedings of the Conference Record of the Forty Sixth Asilomar Conference on Signals, 2012
2011
Tunable Mismatch Shaping for Quadrature Bandpass DeltaSigma Data Converters.
Signal Processing Systems, 2011
A Goldschmidt Division Method With Faster Than Quadratic Convergence.
IEEE Trans. VLSI Syst., 2011
Quantifying academic placer performance on custom designs.
Proceedings of the 2011 International Symposium on Physical Design, 2011
Design rules for Quantumdot Cellular Automata.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2011), 2011
Hybrid residue generators for increased efficiency.
Proceedings of the Conference Record of the Forty Fifth Asilomar Conference on Signals, 2011
The fullyserial pipelined multiplier.
Proceedings of the Conference Record of the Forty Fifth Asilomar Conference on Signals, 2011
A floatingpoint fused FFT butterfly arithmetic unit with Merged MultipleConstant Multipliers.
Proceedings of the Conference Record of the Forty Fifth Asilomar Conference on Signals, 2011
2010
A Reduced Complexity Wallace Multiplier Reduction.
IEEE Trans. Computers, 2010
Adaptive CORDIC: Using Parallel Angle Recoding to Accelerate Rotations.
IEEE Trans. Computers, 2010
Priority Tries for IP Address Lookup.
IEEE Trans. Computers, 2010
A Rounding Method to Reduce the Required Multiplier Precision for Goldschmidt Division.
IEEE Trans. Computers, 2010
High speed recursionfree CORDIC architecture.
Proceedings of the Annual IEEE International SoC Conference, SoCC 2010, 2010
QCA Systolic Matrix Multiplier.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2010
A novel technique for tunable mismatch shaping in oversampled digitaltoanalog converters.
Proceedings of the IEEE International Conference on Acoustics, 2010
2009
Adder and Multiplier Design in QuantumDot Cellular Automata.
IEEE Trans. Computers, 2009
ASIC evaluation of ECHO hash function.
Proceedings of the Annual IEEE International SoC Conference, SoCC 2009, 2009
JavaFlow  A Java dataflow machine.
Proceedings of the Annual IEEE International SoC Conference, SoCC 2009, 2009
Design of a Goldschmidt iterative divider for quantumdot cellular automata.
Proceedings of the 2009 IEEE/ACM International Symposium on Nanoscale Architectures, 2009
A PowerScalable SwitchBased Multiprocessor FFT.
Proceedings of the 20th IEEE International Conference on ApplicationSpecific Systems, 2009
2008
FixedPoint Computer Arithmetic.
Proceedings of the Wiley Encyclopedia of Computer Science and Engineering, 2008
FloatingPoint Computer Arithmetic.
Proceedings of the Wiley Encyclopedia of Computer Science and Engineering, 2008
Systolic FFT Processors: A Personal Perspective.
Signal Processing Systems, 2008
Negative Save Sign Extension for Multiterm Adders and Multipliers.
Signal Processing Systems, 2008
Bridge FloatingPoint Fused MultiplyAdd Design.
IEEE Trans. VLSI Syst., 2008
Speculative Carry Generation With Prefix Adder.
IEEE Trans. VLSI Syst., 2008
High performance IP lookup circuit using DDR SDRAM.
Proceedings of the 21st Annual IEEE International SoC Conference, SoCC 2008, 2008
A floatingpoint fused dotproduct unit.
Proceedings of the 26th International Conference on Computer Design, 2008
32 bit single cycle nonlinear VLSI cell for the ICA algorithm.
Proceedings of the IEEE International Conference on Acoustics, 2008
2007
The Negative Two's Complement Number System.
VLSI Signal Processing, 2007
The HazardFree Superscalar Pipeline Fast Fourier Transform Architecture and Algorithm.
Proceedings of the VLSISoC: Advanced Topics on Systems on a Chip, 2007
The hazardfree superscalar pipeline fast fourier transform algorithm and architecture.
Proceedings of the IFIP VLSISoC 2007, 2007
Contentionfree switchbased implementation of 1024point Radix2 Fourier Transform Engine.
Proceedings of the 25th International Conference on Computer Design, 2007
Serial Parallel Multiplier Design in Quantumdot Cellular Automata.
Proceedings of the 18th IEEE Symposium on Computer Arithmetic (ARITH18 2007), 2007
2006
Digitpipelined direct digital frequency synthesis based on differential CORDIC.
IEEE Trans. on Circuits and Systems, 2006
Systolic FFT Processors: Past, Present and Future.
Proceedings of the 2006 IEEE International Conference on ApplicationSpecific Systems, 2006
Design of Radix4 SRT Dividers in 65 Nanometer CMOS Technology.
Proceedings of the 2006 IEEE International Conference on ApplicationSpecific Systems, 2006
2005
Three Dimensional System on Chip Technology, invited.
Proceedings of the 5th IEEE International Workshop on SystemonChip for RealTime Applications (IWSOC 2005), 2005
MultiplyAccumulate Architecture for a Special Class of Optimal Extension Fields.
Proceedings of the 16th IEEE International Conference on ApplicationSpecific Systems, 2005
Parallel Prefix Adder Design with Matrix Representation.
Proceedings of the 17th IEEE Symposium on Computer Arithmetic (ARITH17 2005), 2005
2004
A Review of Large Parallel Counter Designs.
Proceedings of the 2004 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2004), 2004
Parallel Montgomery Multipliers.
Proceedings of the 15th IEEE International Conference on ApplicationSpecific Systems, 2004
2003
Guest Editorial.
VLSI Signal Processing, 2003
A selftesting method for the pipelined A/D converter.
Proceedings of the 2003 International Symposium on Circuits and Systems, 2003
Quadruple Time Redundancy Adders.
Proceedings of the 18th IEEE International Symposium on Defect and FaultTolerance in VLSI Systems (DFT 2003), 2003
An Architecture for a Radix4 Modular Pipeline Fast Fourier Transform.
Proceedings of the 14th IEEE International Conference on ApplicationSpecific Systems, 2003
2002
A 16Bit by 16Bit MAC Design Using Fast 5: 3 Compressor Cells.
VLSI Signal Processing, 2002
A scaled DCT architecture with the CORDIC algorithm.
IEEE Trans. Signal Processing, 2002
An Analysis of the CORDIC Algorithm for Direct Digital Frequency Synthesis.
Proceedings of the 13th IEEE International Conference on ApplicationSpecific Systems, 2002
Implementation of a Single Chip, Pipelined, Complex, OneDimensional Fast FourierTransform in 0.25 mu m BulkCMOS.
Proceedings of the 13th IEEE International Conference on ApplicationSpecific Systems, 2002
2001
A pipelined architecture for the multidimensional DFT.
IEEE Trans. Signal Processing, 2001
DCT Implementation with Distributed Arithmetic.
IEEE Trans. Computers, 2001
Timeshared TMR for faulttolerant CORDIC processors.
Proceedings of the IEEE International Conference on Acoustics, 2001
A fast hybrid carrylookahead/carryselect adder design.
Proceedings of the 11th ACM Great Lakes Symposium on VLSI 2001, 2001
Enhanced Concurrent Error Correcting Arithmetic Unit Design Using Alternating Logic.
Proceedings of the 16th IEEE International Symposium on Defect and FaultTolerance in VLSI Systems (DFT 2001), 2001
Analysis of Column Compression Multipliers.
Proceedings of the 15th IEEE Symposium on Computer Arithmetic (Arith15 2001), 2001
2000
HighSpeed CORDIC Based on an Overlapped Architecture and a Novel sigmaPrediction Method.
VLSI Signal Processing, 2000
A Family of VariablePrecision Interval Arithmetic Processors.
IEEE Trans. Computers, 2000
A SerialParallel Architecture for TwoDimensional Discrete Cosine and Inverse Discrete Cosine Transforms.
IEEE Trans. Computers, 2000
FaultTolerant NewtonRaphson and Goldschmidt Dividers Using Time Shared TMR.
IEEE Trans. Computers, 2000
FaultTolerant HighPerformance Cordic Processors.
Proceedings of the 15th IEEE International Symposium on Defect and FaultTolerance in VLSI Systems (DFT 2000), 2000
A 16Bit x 16Bit MAC Design Using Fast 5: 2 Compressors.
Proceedings of the 12th IEEE International Conference on ApplicationSpecific Systems, 2000
1999
A parallel implementation of the 2D discrete wavelet transform without interprocessor communications.
IEEE Trans. Signal Processing, 1999
Multidimensional systolic arrays for the implementation of discrete Fourier transforms.
IEEE Trans. Signal Processing, 1999
Parallel Implementation of Multidimensional Transforms without Interprocessor Communication.
IEEE Trans. Computers, 1999
Bipolar merged arithmetic for wavelet architectures.
Proceedings of the 1999 International Symposium on Circuits and Systems, ISCAS 1999, Orlando, Florida, USA, May 30, 1999
HighSpeed CORDIC Architecture Based on Redundant Sum Formation and Overlapped sSelection.
Proceedings of the IEEE International Conference On Computer Design, 1999
TimeShared Modular Redundancy for FaultTolerant FFT Processors.
Proceedings of the 14th International Symposium on Defect and FaultTolerance in VLSI Systems (DFT '99), 1999
Power Consumption in Fast Dividers Using Time Shared TMR.
Proceedings of the 14th International Symposium on Defect and FaultTolerance in VLSI Systems (DFT '99), 1999
1998
Editorial Message.
VLSI Signal Processing, 1998
VLSI, MCM, and WSI: A Design Comparison.
IEEE Design & Test of Computers, 1998
A reduction scheme to optimize the Wallace multiplier.
Proceedings of the International Conference on Computer Design: VLSI in Computers and Processors, 1998
Merged Arithmetic for Computing Wavelet Transforms.
Proceedings of the 8th Great Lakes Symposium on VLSI (GLSVLSI '98), 1998
ErrorCorrecting Goldschmidt Dividers Using Time Shared TMR.
Proceedings of the 13th International Symposium on Defect and FaultTolerance in VLSI Systems (DFT '98), 1998
1997
Hybrid CORDIC Algorithms.
IEEE Trans. Computers, 1997
Calculators.
IEEE Annals of the History of Computing, 1997
Survey of low power techniques for ROMs.
Proceedings of the 1997 International Symposium on Low Power Electronics and Design, 1997
Fast ErrorCorrecting NewtonRaphson Dividers Using Time Shared TMR.
Proceedings of the 1997 Workshop on Defect and FaultTolerance in VLSI Systems (DFT '97), 1997
Realization of a nonlinear digital filter on a DSP array processor.
Proceedings of the 1997 International Conference on ApplicationSpecific Systems, 1997
PowerDelay Characteristics of CMOS Multipliers.
Proceedings of the 13th Symposium on Computer Arithmetic (ARITH13 '97), 1997
1996
A new design for a lookahead carry generator.
VLSI Signal Processing, 1996
Variableprecision, interval arithmetic coprocessors.
Reliable Computing, 1996
Granularlypipelined CORDIC processors for sine and cosine generators.
Proceedings of the 1996 IEEE International Conference on Acoustics, 1996
Multidimensional systolic arrays for multidimensional DFTs.
Proceedings of the 1996 IEEE International Conference on Acoustics, 1996
Comprehensive Modeling of VLSI Test.
Proceedings of the 1996 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 1996
Fault tolerant NewtonRaphson dividers using time shared TMR.
Proceedings of the 1996 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 1996
Finite WordLength Effects Of An Unified Systolic Array For 2D DCT/IDCT.
Proceedings of the 1996 International Conference on ApplicationSpecific Systems, 1996
1995
Parallel reduced area multipliers.
VLSI Signal Processing, 1995
A software interface and hardware design for variableprecision interval arithmetic.
Reliable Computing, 1995
Rapid prototyping faulttolerant heterogeneous digital signal processing systems.
Proceedings of the Sixth IEEE International Workshop on Rapid System Prototyping (RSP '95), 1995
Merged CORDIC Algorithm.
Proceedings of the 1995 IEEE International Symposium on Circuits and Systems, ISCAS 1995, Seattle, Washington, USA, April 30, 1995
FaultTolerant Neural Architectures: The Use of Rotated Operands.
Proceedings of the 1995 IEEE International Symposium on Circuits and Systems, ISCAS 1995, Seattle, Washington, USA, April 30, 1995
TimeRedundant Multiple Computation for FaultTolerant Digital Neural Networks.
Proceedings of the 1995 IEEE International Symposium on Circuits and Systems, ISCAS 1995, Seattle, Washington, USA, April 30, 1995
A coprocessor for accurate and reliable numerical computations.
Proceedings of the 1995 International Conference on Computer Design (ICCD '95), 1995
An efficient systolic array for the discrete cosine transform based on primefactor decomposition .
Proceedings of the 1995 International Conference on Computer Design (ICCD '95), 1995
Characterization and analysis of errors in circuit test.
Proceedings of the 1995 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 1995
Efficient time redundancy for error correcting innerproduct units and convolvers.
Proceedings of the 1995 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 1995
A Processor for Staggered Interval Arithmetic.
Proceedings of the International Conference on Application Specific Array Processors (ASAP'95), 1995
Recomputing by Operand Exchanging: A Timeredundancy Approach for Faulttolerant Neural Networks.
Proceedings of the International Conference on Application Specific Array Processors (ASAP'95), 1995
Hardware Design and Arithmetic Algorithms for a VariablePrecision, Interval Arithmetic Coprocessor.
Proceedings of the 12th Symposium on Computer Arithmetic (ARITH12 '95), 1995
Cascaded Implementation of an Iterative InverseSquareRoot Algorithm, with Overflow Lookahead.
Proceedings of the 12th Symposium on Computer Arithmetic (ARITH12 '95), 1995
1994
Editorial.
VLSI Signal Processing, 1994
Parallel counter implementation.
VLSI Signal Processing, 1994
Fast multiplier bitproduct matrix reduction using bitordering and parity generation.
VLSI Signal Processing, 1994
Hardware Designs for Exactly Rounded Elemantary Functions.
IEEE Trans. Computers, 1994
Boundary scan in board manufacturing.
J. Electronic Testing, 1994
Optimal initial approximations for the NewtonRaphson division algorithm.
Computing, 1994
A Standardized Interface Control Unit for Heterogeneous Digital Signal Processors.
Proceedings of the 1994 IEEE International Symposium on Circuits and Systems, ISCAS 1994, London, England, UK, May 30, 1994
Heterogeneous Parallel Computing.
Proceedings of the Proceedings 1994 International Conference on Parallel and Distributed Systems, 1994
Sorting Networks with BuiltIn Error Correction.
Proceedings of the Proceedings 1994 International Conference on Parallel and Distributed Systems, 1994
Is It Possible to Fairly Compare Interconnection Networks?.
Proceedings of the Proceedings 1994 International Conference on Parallel and Distributed Systems, 1994
What Types of Research Papers Should We Be Writing?
Proceedings of the Proceedings 1994 International Conference on Parallel and Distributed Systems, 1994
A New Asynchronous Multiplier Using Enable/Disable CMOS Differential Logic.
Proceedings of the Proceedings 1994 IEEE International Conference on Computer Design: VLSI in Computer & Processors, 1994
Reliability Estimation for Time Redundant Error Correcting Adders and Multipliers.
Proceedings of the IEEE International Workshop on Defect and Fault Tolerance in VLSI Systems, 1994
A variableprecision interval arithmetic processor.
Proceedings of the International Conference on Application Specific Array Processors, 1994
A systolic array for 2D DFT and 2D DCT.
Proceedings of the International Conference on Application Specific Array Processors, 1994
1993
Modified Booth algorithm for high radix fixedpoint multiplication.
IEEE Trans. VLSI Syst., 1993
Design and implementation of an interface control unit for rapid prototyping.
Proceedings of the Fourth International Workshop on Rapid System Prototyping, 1993
Superpipelined Adder Designs.
Proceedings of the 1993 IEEE International Symposium on Circuits and Systems, 1993
A Comparative Evaluation of Adders Based on Performance and Testability.
Proceedings of the Proceedings 1993 International Conference on Computer Design: VLSI in Computers & Processors, 1993
VLSI Concurrent Error Correcting Adders and Multipliers.
Proceedings of the IEEE International Workshop on Defect and Fault Tolerance in VLSI Systems, 1993
Reduced area multipliers.
Proceedings of the International Conference on ApplicationSpecific Array Processors, 1993
Exact rounding of certain elementary functions.
Proceedings of the 11th Symposium on Computer Arithmetic, 29 June, 1993
Estimating the power consumption of CMOS adders.
Proceedings of the 11th Symposium on Computer Arithmetic, 29 June, 1993
1992
A radix8 wafer scale FFT processor.
VLSI Signal Processing, 1992
A Spanning Tree Carry Lookahead Adder.
IEEE Trans. Computers, 1992
WaferScale Integration: Architectures and Algorithms  Guest Editors' Introduction.
IEEE Computer, 1992
Implementation of Parallel Processors with Wafer Scale Integration.
Proceedings of the 6th International Parallel Processing Symposium, 1992
Modified Booth Algorithm for High Radix Multiplication.
Proceedings of the Proceedings 1992 IEEE International Conference on Computer Design: VLSI in Computer & Processors, 1992
Arithmetic Error Analysis of a new Reciprocal Cell.
Proceedings of the Proceedings 1992 IEEE International Conference on Computer Design: VLSI in Computer & Processors, 1992
1991
Arithmetic for digital neural networks.
Proceedings of the 10th IEEE Symposium on Computer Arithmetic, 1991
Highspeed multiplier design using multiinput counter and compressor circuits.
Proceedings of the 10th IEEE Symposium on Computer Arithmetic, 1991
The redundant cell adder.
Proceedings of the 10th IEEE Symposium on Computer Arithmetic, 1991
1990
Generic signal processor implementation with VHSIC.
VLSI Signal Processing, 1990
1985
Foreword: Advances in Distributed Computing Systems.
IEEE Trans. Software Eng., 1985
VLSI Testing: A Decade of Experience.
Proceedings of the Spring COMPCON'85, 1985
Arithmetic for high speed FFT implementation.
Proceedings of the 7th IEEE Symposium on Computer Arithmetic, 1985
1984
Fast transform processor implementation.
Proceedings of the IEEE International Conference on Acoustics, 1984
1983
Sign/Logarithm Arithmetic for FFT Implementation.
IEEE Trans. Computers, 1983
Digital signal processing with VLSI technology.
Proceedings of the IEEE International Conference on Acoustics, 1983
1982
Supersystems: Technology and Architecture.
IEEE Trans. Computers, 1982
1980
Arithmetic for UltraHighSpeed Tomography.
IEEE Trans. Computers, 1980
Merged Arithmetic.
IEEE Trans. Computers, 1980
Signal processing architectures with VLSI.
Proceedings of the IEEE International Conference on Acoustics, 1980
1979
A Routing Algorithm for Signal Processing Networks.
IEEE Trans. Computers, 1979
Comment on "The Focus Number System".
IEEE Trans. Computers, 1979
Microprogrammed Control for Specialized Processors.
IEEE Trans. Computers, 1979
1978
Inner Product Computers.
IEEE Trans. Computers, 1978
Merged arithmetic for signal processing.
Proceedings of the 4th IEEE Symposium on Computer Arithmetic, 1978
1977
Microprogrammed control for signal processing.
Proceedings of the 10th annual workshop on Microprogramming, 1977
1975
The Sign/Logarithm Number System.
IEEE Trans. Computers, 1975
1973
Review of "Fundamentals of Pattern Recognition" by Edward A. Patrick.
IEEE Trans. Systems, Man, and Cybernetics, 1973
Review of "Introduction to Mathematical Techniques in Pattern Recognition" by Harry C. Andrews.
IEEE Trans. Systems, Man, and Cybernetics, 1973
The inner product computer (Ph.D. Thesis abstr.).
IEEE Trans. Information Theory, 1973
Parallel Counters.
IEEE Trans. Computers, 1973
The QuasiSerial Multiplier.
IEEE Trans. Computers, 1973
Applications of the inner product computer.
Proceedings of the ACM annual conference, Atlanta, Georgia, USA, August 2729, 1973, 1973