Nanako Niioka

According to our database, Nanako Niioka authored at least 6 papers between 2014 and 2015.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2015

Signal Propagation Delay Model in Vertically Stacked Chips.

Nanako Niioka, Masayuki Watanabe, Masa-Aki Fukase, Masashi Imai, Atsushi Kurokawa

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2015

An effective model for evaluating vertical propagation delay in TSV-based 3-D ICs.

Masayuki Watanabe, Nanako Niioka, Tetsuya Kobayashi, Rosely Karel, Masa-Aki Fukase, Masashi Imai, Atsushi Kurokawa

Proceedings of the Sixteenth International Symposium on Quality Electronic Design, 2015

Clock skew reduction for stacked chips using multiple source buffers.

Nanako Niioka, Masashi Imai, Masa-Aki Fukase, Yuuki Miura, Kaoru Furumi, Atsushi Kurokawa

Proceedings of the 15th International Symposium on Communications and Information Technologies, 2015

2014

Effect of substrate contacts on reducing crosstalk noise between TSVs.

Masayuki Watanabe, Rosely Karel, Nanako Niioka, Tetsuya Kobayashi, Masa-Aki Fukase, Masashi Imai, Atsushi Kurokawa

Proceedings of the 2014 IEEE Asia Pacific Conference on Circuits and Systems, 2014

Impact of on-chip interconnects on vertical signal propagation in 3D ICs.

Nanako Niioka, Masayuki Watanabe, Rosely Karel, Tetsuya Kobayashi, Masashi Imai, Masa-Aki Fukase, Atsushi Kurokawa

Proceedings of the 2014 IEEE Asia Pacific Conference on Circuits and Systems, 2014

Modeling of substrate contacts in TSV-based 3D ICs.

Masayuki Watanabe, Masa-Aki Fukase, Masashi Imai, Nanako Niioka, Tetsuya Kobayashi, Rosely Karel, Atsushi Kurokawa

Proceedings of the 2014 International 3D Systems Integration Conference, 2014