Atsushi Kurokawa

According to our database, Atsushi Kurokawa authored at least 66 papers between 2003 and 2023.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2023

Bayesian neural network based inductance calculations of wireless power transfer systems.

Kai Sato, Toshiki Kanamoto, Ryotaro Kudo, Koutaro Hachiya, Atsushi Kurokawa

IEICE Electron. Express, 2023

Electronic component placement optimization for heat measures of smartglasses.

Kyosuke Kusumi, Koutaro Hachiya, Ryotaro Kudo, Toshiki Kanamoto, Atsushi Kurokawa

IEICE Electron. Express, 2023

A parabolic spiral coil transmitter with uniform magnetic field for smart devices.

Ryotaro Kudo, Koutaro Hachiya, Toshiki Kanamoto, Atsushi Kurokawa

IEICE Electron. Express, 2023

A thermally optimizing method of thin film resistor trimming with machine learning.

Taisei Arima, Shigeru Hidaka, Ryosuke Watanabe, Tomoya Akasaka, Atsushi Kurokawa, Toshiki Kanamoto

IEICE Electron. Express, 2023

2022

A bernoulli spiral coil transmitter for charging various small electronic devices.

Ryotaro Kudo, Koutaro Hachiya, Toshiki Kanamoto, Atsushi Kurokawa

IEICE Electron. Express, 2022

Receiver coil built into belt for heat dissipation of watch-type smart devices.

Shinsuke Kashiwazaki, Koutaro Hachiya, Toshiki Kanamoto, Ryosuke Watanabe, Atsushi Kurokawa

IEICE Electron. Express, 2022

Enhanced laser trimming of thin film resistors dedicated to snubber for high power IGBT modules.

Ryosuke Watanabe, Shigeru Hidaka, Tomoya Akasaka, Shota Kajiya, Taisei Arima, Atsushi Kurokawa, Toshiki Kanamoto

Proceedings of the 65th IEEE International Midwest Symposium on Circuits and Systems, 2022

Deep Neural Network Based Inductance Calculations of Wireless Power Transfer Systems.

Kai Sato, Toshiki Kanamoto, Ryotaro Kudo, Koutaro Hachiya, Atsushi Kurokawa

Proceedings of the 11th IEEE Global Conference on Consumer Electronics, 2022

A Parabolic Spiral Coil Transmitter for Charging Multiple Receivers.

Ryotaro Kudo, Koutaro Hachiya, Toshiki Kanamoto, Atsushi Kurokawa

Proceedings of the 11th IEEE Global Conference on Consumer Electronics, 2022

2021

Effective methods to promote heat dissipation of wrist wearables.

Kodai Matsuhashi, Koutaro Hachiya, Toshiki Kanamoto, Shinsuke Kashiwazaki, Kyosuke Kusumi, Atsushi Kurokawa

IEICE Electron. Express, 2021

An Energy Efficient Processor Applicable to Continuous SPO2 Monitoring.

Kan Hatakeyama, Seria Kasai, Masashi Imai, Atsushi Kurokawa, Masami Fukushima, Koichi Kitagishi, Seijin Nakayama, Hideki Ishihara

Proceedings of the 10th IEEE Global Conference on Consumer Electronics, 2021

2020

Thermal Model and Countermeasures for Future Smart Glasses.

Kodai Matsuhashi, Toshiki Kanamoto, Atsushi Kurokawa

Sensors, 2020

Thermal placement on PCB of components including 3D ICs.

Yuuta Satomi, Koutaro Hachiya, Toshiki Kanamoto, Ryosuke Watanabe, Atsushi Kurokawa

IEICE Electron. Express, 2020

A simple yet precise capacitance estimation method for on-chip power delivery network towards EMC analysis.

Toshiki Kanamoto, Koki Kasai, Kan Hatakeyama, Atsushi Kurokawa, Tomoyuki Nagase, Masashi Imai

IEICE Electron. Express, 2020

Testing Through Silicon Vias in Power Distribution Network of 3D-IC with Manufacturing Variability Cancellation.

Koutaro Hachiya, Atsushi Kurokawa

Proceedings of the 2020 Design, Automation & Test in Europe Conference & Exhibition, 2020

2019

A Single-Stage RISC-V Processor to Mitigate the Von Neumann Bottleneck.

Toshiki Kanamoto, Masami Fukushima, Koichi Kitagishi, Seijin Nakayama, Hideki Ishihara, Koki Kasai, Atsushi Kurokawa, Masashi Imai

Proceedings of the 62nd IEEE International Midwest Symposium on Circuits and Systems, 2019

Power Transfer System Combining Wireless Resonators and Wired Three-Coil Repeater.

Motoki Ishizaki, Atsushi Kurokawa

Proceedings of the IEEE International Symposium on Circuits and Systems, 2019

Thermal Countermeasures of Glass Wearable Devices.

Kodai Matsuhashi, Atsushi Kurokawa

Proceedings of the IEEE International Conference on Consumer Electronics - Taiwan, 2019

Repeater Coil Connections for WPT System with Wired Three Coils.

Motoki Ishizaki, Atsushi Kurokawa

Proceedings of the IEEE 8th Global Conference on Consumer Electronics, 2019

Hardware Trojan Insertion and Detection in Asynchronous Circuits.

Koutaro Inaba, Tomohiro Yoneda, Toshiki Kanamoto, Atsushi Kurokawa, Masashi Imai

Proceedings of the 25th IEEE International Symposium on Asynchronous Circuits and Systems, 2019

Advantages and Characteristics of a WPT System with a Resonant Wired-2-Coil Repeater.

Motoki Ishizaki, Atsushi Kurokawa

Proceedings of the IEEE VTS Asia Pacific Wireless Communications Symposium, 2019

Variability Cancellation to Improve Diagnostic Performance of Testing through Silicon Vias in Power Distribution Network of 3D-IC.

Koutaro Hachiya, Atsushi Kurokawa

Proceedings of the 2019 International 3D Systems Integration Conference (3DIC), 2019

2017

Cooling architectures using thermal sidewalls, interchip plates, and bottom plate for 3D ICs.

Kaoru Furumi, Masashi Imai, Atsushi Kurokawa

Proceedings of the 18th International Symposium on Quality Electronic Design, 2017

2015

Signal Propagation Delay Model in Vertically Stacked Chips.

Nanako Niioka, Masayuki Watanabe, Masa-Aki Fukase, Masashi Imai, Atsushi Kurokawa

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2015

Structure optimization for timing in nano scale FinFET.

Toshiki Kanamoto, Takeichiro Akamine, Hiroaki Ammo, Takashi Hasegawa, Kouhei Shimizu, Yoshinori Kumano, Masaharu Kawano, Atsushi Kurokawa

IEICE Electron. Express, 2015

An effective model for evaluating vertical propagation delay in TSV-based 3-D ICs.

Masayuki Watanabe, Nanako Niioka, Tetsuya Kobayashi, Rosely Karel, Masa-Aki Fukase, Masashi Imai, Atsushi Kurokawa

Proceedings of the Sixteenth International Symposium on Quality Electronic Design, 2015

Clock skew reduction for stacked chips using multiple source buffers.

Nanako Niioka, Masashi Imai, Masa-Aki Fukase, Yuuki Miura, Kaoru Furumi, Atsushi Kurokawa

Proceedings of the 15th International Symposium on Communications and Information Technologies, 2015

2014

An Effective Model of the Overshooting Effect for Multiple-Input Gates in Nanometer Technologies.

Li Ding, Zhangcai Huang, Atsushi Kurokawa, Jing Wang, Yasuaki Inoue

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2014

Effect of substrate contacts on reducing crosstalk noise between TSVs.

Masayuki Watanabe, Rosely Karel, Nanako Niioka, Tetsuya Kobayashi, Masa-Aki Fukase, Masashi Imai, Atsushi Kurokawa

Proceedings of the 2014 IEEE Asia Pacific Conference on Circuits and Systems, 2014

Impact of on-chip interconnects on vertical signal propagation in 3D ICs.

Nanako Niioka, Masayuki Watanabe, Rosely Karel, Tetsuya Kobayashi, Masashi Imai, Masa-Aki Fukase, Atsushi Kurokawa

Proceedings of the 2014 IEEE Asia Pacific Conference on Circuits and Systems, 2014

Modeling of substrate contacts in TSV-based 3D ICs.

Masayuki Watanabe, Masa-Aki Fukase, Masashi Imai, Nanako Niioka, Tetsuya Kobayashi, Rosely Karel, Atsushi Kurokawa

Proceedings of the 2014 International 3D Systems Integration Conference, 2014

2013

An analytical model of the overshooting effect for multiple-input gates in nanometer technologies.

Li Ding, Jing Wang, Zhangcai Huang, Atsushi Kurokawa, Yasuaki Inoue

Proceedings of the 2013 IEEE International Symposium on Circuits and Systems (ISCAS2013), 2013

2012

Modeling the Overshooting Effect of Multi-Input gate in Nanometer Technologies.

Li Ding, Zhangcai Huang, Minglu Jiang, Atsushi Kurokawa, Yasuaki Inoue

J. Circuits Syst. Comput., 2012

Optimum design of the execution stage of embedded processors.

Masa-Aki Fukase, Atsushi Kurokawa, Kouhei Ichinohe, Tatsuya Takaki

Proceedings of the International Symposium on Communications and Information Technologies, 2012

2011

A Non-Iterative Method for Calculating the Effective Capacitance of CMOS Gates with Interconnect Load Effect.

Minglu Jiang, Zhangcai Huang, Atsushi Kurokawa, Qiang Li, Bin Lin, Yasuaki Inoue

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2011

Development of a next generation ubiquitous processor chip.

Masa-Aki Fukase, Harunobu Uchiumi, Kazuki Narita, Tatsuya Takaki, Naomichi Mimura, Kohei Ichinohe, Tomoaki Sato, Atsushi Kurokawa

Proceedings of the International Symposium on Intelligent Signal Processing and Communications Systems, 2011

2010

Modeling the Overshooting Effect for CMOS Inverter Delay Analysis in Nanometer Technologies.

Zhangcai Huang, Atsushi Kurokawa, Masanori Hashimoto, Takashi Sato, Minglu Jiang, Yasuaki Inoue

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2010

Simple Analytical Formulas for Estimating IR-Drops in an Early Design Stage.

Kazuyuki Ooya, Yuji Takashima, Atsushi Kurokawa

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2010

Impact of Self-Heating in Wire Interconnection on Timing.

Toshiki Kanamoto, Takaaki Okumura, Katsuhiro Furukawa, Hiroshi Takafuji, Atsushi Kurokawa, Koutaro Hachiya, Tsuyoshi Sakata, Masakazu Tanaka, Hidenari Nakashima, Hiroo Masuda, Takashi Sato, Masanori Hashimoto

IEICE Trans. Electron., 2010

2009

Practical Redundant-Via Insertion Method Considering Manufacturing Variability and Reliability.

Yuji Takashima, Kazuyuki Ooya, Atsushi Kurokawa

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2009

An Approach for Reducing Leakage Current Variation due to Manufacturing Variability.

Tsuyoshi Sakata, Takaaki Okumura, Atsushi Kurokawa, Hidenari Nakashima, Hiroo Masuda, Takashi Sato, Masanori Hashimoto, Koutaro Hachiya, Katsuhiro Furukawa, Masakazu Tanaka, Hiroshi Takafuji, Toshiki Kanamoto

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2009

Improvement in Computational Accuracy of Output Transition Time Variation Considering Threshold Voltage Variations.

Takaaki Okumura, Atsushi Kurokawa, Hiroo Masuda, Toshiki Kanamoto, Masanori Hashimoto, Hiroshi Takafuji, Hidenari Nakashima, Nobuto Ono, Tsuyoshi Sakata, Takashi Sato

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2009

Accurate Method for Calculating the Effective Capacitance with RC Loads Based on the Thevenin Model.

Minglu Jiang, Zhangcai Huang, Atsushi Kurokawa, Shuai Fang, Yasuaki Inoue

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2009

2008

Prevention in a Chip of EMI Noise Caused by X'tal Oscillator.

Atsushi Kurokawa, Hiroshi Fujita, Tetsuya Ibe

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2008

2007

Modeling the Overshooting Effect for CMOS Inverter in Nanometer Technologies.

Zhangcai Huang, Hong Yu, Atsushi Kurokawa, Yasuaki Inoue

Proceedings of the 12th Conference on Asia South Pacific Design Automation, 2007

2006

Determination of Interconnect Structural Parameters for Best- and Worst-Case Delays.

Atsushi Kurokawa, Hiroo Masuda, Junko Fujii, Toshinori Inoshita, Akira Kasebe, Zhangcai Huang, Yasuaki Inoue

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2006

Formula-Based Method for Capacitance Extraction of Interconnects with Dummy Fills.

Atsushi Kurokawa, Akira Kasebe, Toshiki Kanamoto, Yun Yang, Zhangcai Huang, Yasuaki Inoue, Hiroo Masuda

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2006

Impact of Intrinsic Parasitic Extraction Errors on Timing and Noise Estimation.

Toshiki Kanamoto, Shigekiyo Akutsu, Tamiyo Nakabayashi, Takahiro Ichinomiya, Koutaro Hachiya, Atsushi Kurokawa, Hiroshi Ishikawa, Sakae Muromoto, Hiroyuki Kobayashi, Masanori Hashimoto

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2006

Modeling the Influence of Input-to-Output Coupling Capacitance on CMOS Inverter Delay.

Zhangcai Huang, Atsushi Kurokawa, Yun Yang, Hong Yu, Yasuaki Inoue

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2006

A gate delay model focusing on current fluctuation over wide-range of process and environmental variability.

Kenichi Shinkai, Masanori Hashimoto, Atsushi Kurokawa, Takao Onoye

Proceedings of the 2006 International Conference on Computer-Aided Design, 2006

2005

Efficient Large Scale Integration Power/Ground Network Optimization Based on Grid Genetic Algorithm.

Yun Yang, Atsushi Kurokawa, Yasuaki Inoue, Wenqing Zhao

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2005

A Practical Approach for Efficiently Extracting Interconnect Capacitances with Floating Dummy Fills.

Atsushi Kurokawa, Toshiki Kanamoto, Akira Kasebe, Yasuaki Inoue, Hiroo Masuda

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2005

Efficient Dummy Filling Methods to Reduce Interconnect Capacitance and Number of Dummy Metal Fills.

Atsushi Kurokawa, Toshiki Kanamoto, Tetsuya Ibe, Akira Kasebe, Wei Fong Chang, Tetsuro Kage, Yasuaki Inoue, Hiroo Masuda

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2005

Second-Order Polynomial Expressions for On-Chip Interconnect Capacitance.

Atsushi Kurokawa, Masanori Hashimoto, Akira Kasebe, Zhangcai Huang, Yun Yang, Yasuaki Inoue, Ryosuke Inagaki, Hiroo Masuda

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2005

Modeling the Effective Capacitance of Interconnect Loads for Predicting CMOS Gate Slew.

Zhangcai Huang, Atsushi Kurokawa, Jun Pan, Yasuaki Inoue

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2005

A Novel Model for Computing the Effective Capacitance of CMOS Gates with Interconnect Loads.

Zhangcai Huang, Atsushi Kurokawa, Yasuaki Inoue, Junfa Mao

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2005

Capacitance and Yield Evaluations Using a 90-nm Process Technology Based on the Dense Power-Ground Interconnect Architecture.

Atsushi Kurokawa, Masaharu Yamamoto, Nobuto Ono, Tetsuro Kage, Yasuaki Inoue, Hiroo Masuda

Proceedings of the 6th International Symposium on Quality of Electronic Design (ISQED 2005), 2005

Dummy Filling Methods for Reducing Interconnect Capacitance and Number of Fills.

Atsushi Kurokawa, Toshiki Kanamoto, Tetsuya Ibe, Akira Kasebe, Wei Fong Chang, Tetsuro Kage, Yasuaki Inoue, Hiroo Masuda

Proceedings of the 6th International Symposium on Quality of Electronic Design (ISQED 2005), 2005

Effective capacitance for gate delay with RC loads.

Zhangcai Huang, Atsushi Kurokawa, Yasuaki Inoue

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005

Challenge: variability characterization and modeling for 65- to 90-nm processes.

Hiroo Masuda, Shin-ichi Ohkawa, Atsushi Kurokawa, Masakazu Aoki

Proceedings of the IEEE 2005 Custom Integrated Circuits Conference, 2005

2004

Efficient capacitance extraction method for interconnects with dummy fills.

Atsushi Kurokawa, Toshiki Kanamoto, Akira Kasebe, Yasuaki Inoue, Hiroo Masuda

Proceedings of the IEEE 2004 Custom Integrated Circuits Conference, 2004

DEPOGIT: dense power-ground interconnect architecture for physical design integrity.

Atsushi Kurokawa, Nobuto Ono, Tetsuro Kage, Hiroo Masuda

Proceedings of the 2004 Conference on Asia South Pacific Design Automation: Electronic Design and Solution Fair 2004, 2004

2003

Approximation Formula Approach for the Efficient Extraction of On-Chip Mutual Inductances.

Atsushi Kurokawa, Takashi Sato, Hiroo Masuda

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2003

Fast On-Chip Inductance Extraction of VLSI Including Angled Interconnects.

Atsushi Kurokawa, Kotaro Hachiya, Takashi Sato, Kazuya Tokumasu, Hiroo Masuda

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2003

Accurate prediction of the impact of on-chip inductance on interconnect delay using electrical and physical parameter-based RSF.

Takashi Sato, Toshiki Kanamoto, Atsushi Kurokawa, Yoshiyuki Kawakami, Hiroki Oka, Tomoyasu Kitaura, Hiroyuki Kobayashi, Masanori Hashimoto

Proceedings of the 2003 Asia and South Pacific Design Automation Conference, 2003

Approximate formulae approach for efficient inductance extraction.

Atsushi Kurokawa, Takashi Sato, Hiroo Masuda

Proceedings of the 2003 Asia and South Pacific Design Automation Conference, 2003