Narain D. Arora

According to our database1, Narain D. Arora authored at least 4 papers between 1993 and 2007.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Dataset
Other 

Links

On csauthors.net:

Bibliography

2007
On-Chip Inductance in X Architecture Enabled Design.
Proceedings of the 8th International Symposium on Quality of Electronic Design (ISQED 2007), 2007

MOSFET Modeling for VLSI Simulation - Theory and Practice
International Series on Advances in Solid State Electronics and Technology, World Scientific, ISBN: 978-981-4365-49-9, 2007

1996
Modeling and extraction of interconnect capacitances for multilayer VLSI circuits.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1996

1993
OPTIMA: A nonlinear model parameter extraction program with statistical confidence region algorithms.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1993


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