Arani Sinha

Orcid: 0000-0003-2069-3177

According to our database1, Arani Sinha authored at least 28 papers between 1994 and 2023.

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Bibliography

2023
Maximizing Stress Coverage by Novel DFT Techniques and Relaxed Timing Closure.
Proceedings of the IEEE International Test Conference, 2023

2022
Innovative Practices Track: Next Generation Test Standards.
Proceedings of the 40th IEEE VLSI Test Symposium, 2022

Innovative Practices Track: Silent Data Errors.
Proceedings of the 40th IEEE VLSI Test Symposium, 2022

Multi-die Parallel Test Fabric for Scalability and Pattern Reusability.
Proceedings of the IEEE International Test Conference, 2022

Using Fault Detection Tests to Produce Diagnostic Tests Targeting Large Sets of Candidate Faults.
Proceedings of the IEEE 31st Asian Test Symposium, 2022

2021
Two Pattern Timing Tests Capturing Defect-Induced Multi-Gate Delay Impact of Shorts.
Proceedings of the 39th IEEE VLSI Test Symposium, 2021

Synergies Between Delay Test and Post-silicon Speed Path Validation: A Tutorial Introduction.
Proceedings of the 26th IEEE European Test Symposium, 2021

2020
Silicon-Proven Timing Signoff Methodology Using Hazard-Free Robust Path Delay Tests.
IEEE Des. Test, 2020

SAT-ATPG Generated Multi-Pattern Scan Tests for Cell Internal Defects: Coverage Analysis for Resistive Opens and Shorts.
Proceedings of the IEEE International Test Conference, 2020

2019
Layout Resynthesis by Applying Design-for-manufacturability Guidelines to Avoid Low-coverage Areas of a Cell-based Design.
ACM Trans. Design Autom. Electr. Syst., 2019

Analog/Mixed Signal IP DFx from a Foundry perspective.
Proceedings of the IEEE Latin American Test Symposium, 2019

Characterization of Library Cells for Open-circuit Defect Exposure: A Systematic Methodology.
Proceedings of the IEEE International Test Conference, 2019

Resynthesis for Avoiding Undetectable Faults Based on Design-for-Manufacturability Guidelines.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2019

2017
Innovative practices session 1C screening for layout sensitive defects.
Proceedings of the 35th IEEE VLSI Test Symposium, 2017

DFM-aware fault model and ATPG for intra-cell and inter-cell defects.
Proceedings of the IEEE International Test Conference, 2017

2013
Path selection based on static timing analysis considering input necessary assignments.
Proceedings of the 31st IEEE VLSI Test Symposium, 2013

2011
The bang for the buck with resiliency: Yield or field?
Proceedings of the 29th IEEE VLSI Test Symposium, 2011

The buck stops with wafer test: Dream or reality?
Proceedings of the 29th IEEE VLSI Test Symposium, 2011

A Novel mechanism for speed characterization during delay test.
Proceedings of the 29th IEEE VLSI Test Symposium, 2011

2010
Special session 8C: Panel EDA for analog DFT/ATPG - will SoC cost pressures make this a reality?
Proceedings of the 28th IEEE VLSI Test Symposium, 2010

2009
Panel: Analog Characterization and Test: The Long Road to Realization.
Proceedings of the 27th IEEE VLSI Test Symposium, 2009

2008
A Multi-valued Algebra for Capacitance Induced Crosstalk Delay Faults.
Proceedings of the 17th IEEE Asian Test Symposium, 2008

2007
On-Chip Inductance in X Architecture Enabled Design.
Proceedings of the 8th International Symposium on Quality of Electronic Design (ISQED 2007), 2007

2006
Simulating the Effects of Process Variations on Capacitive Crosstalk.
Proceedings of the 13th IEEE International Conference on Electronics, 2006

2003
An Enhanced Test Generator for Capacitance Induced Crosstalk Delay Faults.
Proceedings of the 12th Asian Test Symposium (ATS 2003), 17-19 November 2003, Xian, China, 2003

1999
Validation and test generation for oscillatory noise in VLSI interconnects.
Proceedings of the 1999 IEEE/ACM International Conference on Computer-Aided Design, 1999

Mesh-structured on-chip power/ground: design for minimum inductance and characterization for fast R, L extraction.
Proceedings of the IEEE 1999 Custom Integrated Circuits Conference, 1999

1994
Location of the Largest Empty Rectangle among Arbitrary Obstacles.
Proceedings of the Foundations of Software Technology and Theoretical Computer Science, 1994


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