Naresh Maheshwari

According to our database1, Naresh Maheshwari authored at least 7 papers between 1996 and 1999.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

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PhD thesis 
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Links

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Bibliography

1999
Optimizing large multiphase level-clocked circuits.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1999

Retiming control logic.
Integr., 1999

1998
Efficient retiming of large circuits.
IEEE Trans. Very Large Scale Integr. Syst., 1998

Efficient Minarea Retiming of Large Level-Clocked Circuits.
Proceedings of the 1998 Design, 1998

1997
Minimum area retiming with equivalent initial states.
Proceedings of the 1997 IEEE/ACM International Conference on Computer-Aided Design, 1997

An Improved Algorithm for Minimum-Area Retiming.
Proceedings of the 34st Conference on Design Automation, 1997

1996
A Practical Algorithm for Retiming Level-Clocked Circuits.
Proceedings of the 1996 International Conference on Computer Design (ICCD '96), 1996


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