Sachin S. Sapatnekar

According to our database1, Sachin S. Sapatnekar authored at least 331 papers between 1991 and 2020.

Collaborative distances:

Awards

ACM Fellow

ACM Fellow 2016, "For contributions to the enhancement of performance and reliability in integrated circuits".

IEEE Fellow

IEEE Fellow 2003, "For contributions to the optimization of timing and layout in VLSI circuits.".

Timeline

Legend:

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PhD thesis 
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Homepages:

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Bibliography

2020
NeuPart: Using Analytical Models to Drive Energy-Efficient Partitioning of CNN Computations on Cloud-Connected Mobile Clients.
IEEE Trans. Very Large Scale Integr. Syst., 2020

Adaptive-Length Coding of Image Data for Low-Cost Approximate Storage.
IEEE Trans. Computers, 2020

PIMBALL: Binary Neural Networks in Spintronic Memory.
ACM Trans. Archit. Code Optim., 2020

Thermal and IR Drop Analysis Using Convolutional Encoder-Decoder Networks.
CoRR, 2020

ALIGN: A System for Automating Analog Layout.
CoRR, 2020

An Inference and Learning Engine for Spiking Neural Networks in Computational RAM (CRAM).
CoRR, 2020

Exploring a Machine Learning Approach to Performance Driven Analog IC Placement.
Proceedings of the 2020 IEEE Computer Society Annual Symposium on VLSI, 2020

Stress-Induced Performance Shifts in Flexible System-in-Foils Using Ultra-Thin Chips.
Proceedings of the 21st International Symposium on Quality Electronic Design, 2020

Learning from Experience: Applying ML to Analog Circuit Design.
Proceedings of the ISPD 2020: International Symposium on Physical Design, Taipei, Taiwan, March 29, 2020

GANA: Graph Convolutional Network Based Automated Netlist Annotation for Analog Circuits.
Proceedings of the 2020 Design, Automation & Test in Europe Conference & Exhibition, 2020

Template-based PDN Synthesis in Floorplan and Placement Using Classifier and CNN Techniques.
Proceedings of the 25th Asia and South Pacific Design Automation Conference, 2020

2019
Stress-Induced Performance Shifts in 3D DRAMs.
ACM Trans. Design Autom. Electr. Syst., 2019

Dynamic Approximation of JPEG Hardware.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2019

An Analytical Approach for Error PMF Characterization in Approximate Circuits.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2019

In-Memory Processing on the Spintronic CRAM: From Hardware Design to Application Mapping.
IEEE Trans. Computers, 2019

A Machine Learning Accelerator In-Memory for Energy Harvesting.
CoRR, 2019

Improving QoS for Global Dual-Criticality Scheduling on Multiprocessors.
Proceedings of the 25th IEEE International Conference on Embedded and Real-Time Computing Systems and Applications, 2019

A 40×40 Four-Neighbor Time-Based In-Memory Computing Graph ASIC Chip Featuring Wavefront Expansion and 2D Gradient Control.
Proceedings of the IEEE International Solid- State Circuits Conference, 2019

Using Spin-Hall MTJs to Build an Energy-Efficient In-memory Computation Platform.
Proceedings of the 20th International Symposium on Quality Electronic Design, 2019

Fast Mapping-Based High-Level Synthesis of Pipelined Circuits.
Proceedings of the 20th International Symposium on Quality Electronic Design, 2019

Impact of Self-heating on Performance and Reliability in FinFET and GAAFET Designs.
Proceedings of the 20th International Symposium on Quality Electronic Design, 2019

Electromigration-Aware Interconnect Design.
Proceedings of the 2019 International Symposium on Physical Design, 2019

Reliability Analysis of a Delay-Locked Loop Under HCI and BTI Degradation.
Proceedings of the IEEE International Reliability Physics Symposium, 2019

Using DCT-based Approximate Communication to Improve MPI Performance in Parallel Clusters.
Proceedings of the 38th IEEE International Performance Computing and Communications Conference, 2019

True In-memory Computing with the CRAM: From Technology to Applications.
Proceedings of the 2019 on Great Lakes Symposium on VLSI, 2019

An Energy Efficient Non-Volatile Flip-Flop based on CoMET Technology.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2019

ALIGN: Open-Source Analog Layout Automation from the Ground Up.
Proceedings of the 56th Annual Design Automation Conference 2019, 2019

Toward an Open-Source Digital Flow: First Learnings from the OpenROAD Project.
Proceedings of the 56th Annual Design Automation Conference 2019, 2019

SeFAct: selective feature activation and early classification for CNNs.
Proceedings of the 24th Asia and South Pacific Design Automation Conference, 2019

Error Analysis and Optimization in Approximate Arithmetic Circuits.
Proceedings of the Approximate Circuits, Methodologies and CAD., 2019

2018
A Simple Yet Efficient Accuracy-Configurable Adder Design.
IEEE Trans. Very Large Scale Integr. Syst., 2018

Circuit Performance Shifts Due to Layout-Dependent Stress in Planar and 3D-ICs.
IEEE Trans. Very Large Scale Integr. Syst., 2018

Computational RAM to Accelerate String Matching at Scale.
CoRR, 2018

Exploiting Processing in Non-Volatile Memory for Binary Neural Network Accelerators.
CoRR, 2018

SkyLogic - A proposal for a skyrmion logic device.
CoRR, 2018

Efficient In-Memory Processing Using Spintronics.
IEEE Comput. Archit. Lett., 2018

Plenaries.
Proceedings of the 15th International Conference on Synthesis, 2018

Graceful Degradation of Low-Criticality Tasks in Multiprocessor Dual-Criticality Systems.
Proceedings of the 26th International Conference on Real-Time Networks and Systems, 2018

Strain-aware performance evaluation and correction for OTFT-based flexible displays.
Proceedings of the International Conference on Computer-Aided Design, 2018

Computing-in-memory with spintronics.
Proceedings of the 2018 Design, Automation & Test in Europe Conference & Exhibition, 2018

Using imprecise computing for improved non-preemptive real-time scheduling.
Proceedings of the 55th Annual Design Automation Conference, 2018

2017
Fast Stochastic Analysis of Electromigration in Power Distribution Networks.
IEEE Trans. Very Large Scale Integr. Syst., 2017

Estimating Circuit Aging Due to BTI and HCI Using Ring-Oscillator-Based Sensors.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2017

Probabilistic Wire Resistance Degradation Due to Electromigration in Power Grids.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2017

Cost-quality trade-offs of approximate memory repair mechanisms for image data.
Proceedings of the 18th International Symposium on Quality Electronic Design, 2017

Stress-aware performance evaluation of 3D-stacked wide I/O DRAMs.
Proceedings of the 2017 IEEE/ACM International Conference on Computer-Aided Design, 2017

Advanced spintronic memory and logic for non-volatile processors.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2017

A Pathway to Enable Exponential Scaling for the Beyond-CMOS Era: Invited.
Proceedings of the 54th Annual Design Automation Conference, 2017

SABER: Selection of Approximate Bits for the Design of Error Tolerant Circuits.
Proceedings of the 54th Annual Design Automation Conference, 2017

Incorporating the Role of Stress on Electromigration in Power Grids with Via Arrays.
Proceedings of the 54th Annual Design Automation Conference, 2017

A quantifiable approach to approximate computing: special session.
Proceedings of the 2017 International Conference on Compilers, 2017

2016
Statistical Timing Analysis.
Encyclopedia of Algorithms, 2016

Power Grid Analysis.
Encyclopedia of Algorithms, 2016

A Fast and Retargetable Framework for Logic-IP-Internal Electromigration Assessment Comprehending Advanced Waveform Effects.
IEEE Trans. Very Large Scale Integr. Syst., 2016

Cell-Internal Electromigration: Analysis and Pin Placement Based Optimization.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2016

Optimized Standard Cells for All-Spin Logic.
ACM J. Emerg. Technol. Comput. Syst., 2016

CoMET: Composite-Input Magnetoelectric-based Logic Technology.
CoRR, 2016

STEM: A Scheme for Two-phase Evaluation of Majority Logic.
CoRR, 2016

Control synthesis and delay sensor deployment for efficient ASV designs.
Proceedings of the 35th International Conference on Computer-Aided Design, 2016

Optimal design of JPEG hardware under the approximate computing paradigm.
Proceedings of the 53rd Annual Design Automation Conference, 2016

Invited - Optimizing device reliability effects at the intersection of physics, circuits, and architecture.
Proceedings of the 53rd Annual Design Automation Conference, 2016

Predicting electromigration mortality under temperature and product lifetime specifications.
Proceedings of the 53rd Annual Design Automation Conference, 2016

Ring Oscillator Clocks and Margins.
Proceedings of the 22nd IEEE International Symposium on Asynchronous Circuits and Systems, 2016

Logic and memory design using spin-based circuits.
Proceedings of the 21st Asia and South Pacific Design Automation Conference, 2016

2015
A Holistic Analysis of Circuit Performance Variations in 3-D ICs With Thermal and TSV-Induced Stress Considerations.
IEEE Trans. Very Large Scale Integr. Syst., 2015

Spin-Based Computing: Device Concepts, Current Status, and a Case Study on a High-Performance Microprocessor.
Proceedings of the IEEE, 2015

RTL Synthesis: From Logic Synthesis to Automatic Pipelining.
Proceedings of the IEEE, 2015

Reducing the signal Electromigration effects on different logic gates by cell layout optimization.
Proceedings of the IEEE 6th Latin American Symposium on Circuits & Systems, 2015

Circuit delay variability due to wire resistance evolution under AC electromigration.
Proceedings of the IEEE International Reliability Physics Symposium, 2015

Stochastic and topologically aware electromigration analysis for clock skew.
Proceedings of the IEEE International Reliability Physics Symposium, 2015

Impact on performance, power, area and wirelength using electromigration-aware cells.
Proceedings of the 2015 IEEE International Conference on Electronics, 2015

Reactive clocks with variability-tracking jitter.
Proceedings of the 33rd IEEE International Conference on Computer Design, 2015

FEMTO: Fast Error Analysis in Multipliers through Topological Traversal.
Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, 2015

Optimization of FinFET-based circuits using a dual gate pitch technique.
Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, 2015

Joint precision optimization and high level synthesis for approximate computing.
Proceedings of the 52nd Annual Design Automation Conference, 2015

A retargetable and accurate methodology for logic-IP-internal electromigration assessment.
Proceedings of the 20th Asia and South Pacific Design Automation Conference, 2015

2014
Distributed On-Chip Switched-Capacitor DC-DC Converters Supporting DVFS in Multicore Systems.
IEEE Trans. Very Large Scale Integr. Syst., 2014

Variation-Aware Variable Latency Design.
IEEE Trans. Very Large Scale Integr. Syst., 2014

Incorporating Hot-Carrier Injection Effects Into Timing Analysis for Large Circuits.
IEEE Trans. Very Large Scale Integr. Syst., 2014

Techniques for scalable and effective routability evaluation.
ACM Trans. Design Autom. Electr. Syst., 2014

Incremental Analysis of Power Grids Using Backward Random Walks.
ACM Trans. Design Autom. Electr. Syst., 2014

Leakage Modeling for Devices with Steep Sub-threshold Slope Considering Random Threshold Variations.
Proceedings of the 2014 27th International Conference on VLSI Design and 2014 13th International Conference on Embedded Systems, 2014

Energy-Efficient Time-Division Multiplexed Hybrid-Switched NoC for Heterogeneous Multicore Systems.
Proceedings of the 2014 IEEE 28th International Parallel and Distributed Processing Symposium, 2014

Analyzing the electromigration effects on different metal layers and different wire lengths.
Proceedings of the 21st IEEE International Conference on Electronics, Circuits and Systems, 2014

ReSCALE: recalibrating sensor circuits for aging and lifetime estimation under BTI.
Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, 2014

A systematic approach for analyzing and optimizing cell-internal signal electromigration.
Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, 2014

Improving STT-MRAM density through multibit error correction.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2014

Predicting circuit aging using ring oscillators.
Proceedings of the 19th Asia and South Pacific Design Automation Conference, 2014

2013
Employing circadian rhythms to enhance power and reliability.
ACM Trans. Design Autom. Electr. Syst., 2013

What happens when circuits grow old: Aging issues in CMOS design.
Proceedings of the 2013 International Symposium on VLSI Design, Automation, and Test, 2013

The impact of shallow trench isolation effects on circuit performance.
Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, 2013

Placement optimization of power supply pads based on locality.
Proceedings of the Design, Automation and Test in Europe, 2013

CATALYST: planning layer directives for effective design closure.
Proceedings of the Design, Automation and Test in Europe, 2013

The impact of electromigration in copper interconnects on power grid integrity.
Proceedings of the 50th Annual Design Automation Conference 2013, 2013

2012
Compact Current Source Models for Timing Analysis Under Temperature and Body Bias Variations.
IEEE Trans. Very Large Scale Integr. Syst., 2012

Scalable Methods for Analyzing the Circuit Failure Probability Due to Gate Oxide Breakdown.
IEEE Trans. Very Large Scale Integr. Syst., 2012

Optimized 3D Network-on-Chip Design Using Simulated Allocation.
ACM Trans. Design Autom. Electr. Syst., 2012

Fast poisson solvers for thermal analysis.
ACM Trans. Design Autom. Electr. Syst., 2012

Editorial.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2012

Process and Reliability Sensors for Nanoscale CMOS.
IEEE Des. Test Comput., 2012

Energy-efficient non-minimal path on-chip interconnection network for heterogeneous systems.
Proceedings of the International Symposium on Low Power Electronics and Design, 2012

Residential task scheduling under dynamic pricing using the multiple knapsack method.
Proceedings of the IEEE PES Innovative Smart Grid Technologies Conference, 2012

Optimization of on-chip switched-capacitor DC-DC converters for high-performance applications.
Proceedings of the 2012 IEEE/ACM International Conference on Computer-Aided Design, 2012

A holistic analysis of circuit timing variations in 3D-ICs with thermal and TSV-induced stress considerations.
Proceedings of the 2012 IEEE/ACM International Conference on Computer-Aided Design, 2012

Circuit reliability: From Physics to Architectures: Embedded tutorial paper.
Proceedings of the 2012 IEEE/ACM International Conference on Computer-Aided Design, 2012

GLARE: global and local wiring aware routability evaluation.
Proceedings of the 49th Annual Design Automation Conference 2012, 2012

Staggered Core Activation: A circuit/architectural approach for mitigating resonant supply noise issues in multi-core multi-power domain processors.
Proceedings of the IEEE 2012 Custom Integrated Circuits Conference, 2012

BTI-aware design using variable latency units.
Proceedings of the 17th Asia and South Pacific Design Automation Conference, 2012

GNOMO: Greater-than-NOMinal Vdd operation for BTI mitigation.
Proceedings of the 17th Asia and South Pacific Design Automation Conference, 2012

The impact of hot carriers on timing in large circuits.
Proceedings of the 17th Asia and South Pacific Design Automation Conference, 2012

Incremental power network analysis using backward random walks.
Proceedings of the 17th Asia and South Pacific Design Automation Conference, 2012

2011
Adaptive Techniques for Overcoming Performance Degradation Due to Aging in CMOS Circuits.
IEEE Trans. Very Large Scale Integr. Syst., 2011

Overcoming Variations in Nanometer-Scale Technologies.
IEEE J. Emerg. Sel. Topics Circuits Syst., 2011

NoC frequency scaling with flexible-pipeline routers.
Proceedings of the 2011 International Symposium on Low Power Electronics and Design, 2011

The whys and hows of thermal management.
Proceedings of the 2011 International Symposium on Low Power Electronics and Design, 2011

Enabling improved power management in multicore processors through clustered DVFS.
Proceedings of the Design, Automation and Test in Europe, 2011

A scaled random walk solver for fast power grid analysis.
Proceedings of the Design, Automation and Test in Europe, 2011

Thermal signature: a simple yet accurate thermal index for floorplan optimization.
Proceedings of the 48th Design Automation Conference, 2011

Exploration of on-chip switched-capacitor DC-DC converter for multicore processors using a distributed power delivery network.
Proceedings of the 2011 IEEE Custom Integrated Circuits Conference, 2011

Accounting for inherent circuit resilience and process variations in analyzing gate oxide reliability.
Proceedings of the 16th Asia South Pacific Design Automation Conference, 2011

Statistical Design of Integrated Circuits.
Proceedings of the Low-Power Variation-Tolerant Design in Nanometer Silicon, 2011

2010
Capturing Post-Silicon Variations Using a Representative Critical Path.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2010

Scalable methods for the analysis and optimization of gate oxide breakdown.
Proceedings of the 11th International Symposium on Quality of Electronic Design (ISQED 2010), 2010

Dummy fill optimization for enhanced manufacturability.
Proceedings of the 2010 International Symposium on Physical Design, 2010

Adding a new dimension to physical design.
Proceedings of the 2010 International Symposium on Physical Design, 2010

Fast Poisson solvers for thermal analysis.
Proceedings of the 2010 International Conference on Computer-Aided Design, 2010

Application-specific 3D Network-on-Chip design using simulated allocation.
Proceedings of the 15th Asia South Pacific Design Automation Conference, 2010

Physical design techniques for optimizing RTA-induced variations.
Proceedings of the 15th Asia South Pacific Design Automation Conference, 2010

Current source modeling in the presence of body bias.
Proceedings of the 15th Asia South Pacific Design Automation Conference, 2010

Incremental solution of power grids using random walks.
Proceedings of the 15th Asia South Pacific Design Automation Conference, 2010

2009
A Progressive-ILP-Based Routing Algorithm for the Synthesis of Cross-Referencing Biochips.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2009

Fast and Accurate Statistical Criticality Computation Under Process Variations.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2009

A Framework for Scalable Postsilicon Statistical Delay Prediction Under Process Variations.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2009

Optimizing Decoupling Capacitors in 3D Circuits for Power Grid Integrity.
IEEE Des. Test Comput., 2009

Technical perspective - Where the chips may fall.
Commun. ACM, 2009

Synthesizing a representative critical path for post-silicon delay prediction.
Proceedings of the 2009 International Symposium on Physical Design, 2009

Congestion-aware power grid optimization for 3D circuits using MIM and CMOS decoupling capacitors.
Proceedings of the 14th Asia South Pacific Design Automation Conference, 2009

Addressing thermal and power delivery bottlenecks in 3D circuits.
Proceedings of the 14th Asia South Pacific Design Automation Conference, 2009

Adaptive techniques for overcoming performance degradation due to aging in digital circuits.
Proceedings of the 14th Asia South Pacific Design Automation Conference, 2009

2008
Metrics Used in Physical Design.
Proceedings of the Handbook of Algorithms for Physical Design Automation., 2008

Physical Design for Three-Dimensional Circuits.
Proceedings of the Handbook of Algorithms for Physical Design Automation., 2008

Introduction to Physical Design.
Proceedings of the Handbook of Algorithms for Physical Design Automation., 2008

Body Bias Voltage Computations for Process and Temperature Compensation.
IEEE Trans. Very Large Scale Integr. Syst., 2008

Stack Sizing for Optimal Current Drivability in Subthreshold Circuits.
IEEE Trans. Very Large Scale Integr. Syst., 2008

Statistical Leakage Estimation of Double Gate FinFET Devices Considering the Width Quantization Property.
IEEE Trans. Very Large Scale Integr. Syst., 2008

A Scalable Statistical Static Timing Analyzer Incorporating Correlated Non-Gaussian and Gaussian Parameter Variations.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2008

A Geometric Programming-Based Worst Case Gate Sizing Method Incorporating Spatial Correlation.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2008

Technology Mapping Using Logical Effort for Solving the Load-Distribution Problem.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2008

Stochastic Preconditioning for Diagonally Dominant Matrices.
SIAM J. Sci. Comput., 2008

Automated module assignment in stacked-Vdd designs for high-efficiency power delivery.
ACM J. Emerg. Technol. Comput. Syst., 2008

Variability and Statistical Design.
IPSJ Trans. System LSI Design Methodology, 2008

Buffering global interconnects in structured ASIC design.
Integr., 2008

Thermally Aware Design.
Found. Trends Electron. Des. Autom., 2008

Adapting to the times [review of Adaptive Techniques for Dynamic Processor Optimization: Theory and Practice (Wang, A. and Naffziger, S., Eds.; 2008)].
IEEE Des. Test Comput., 2008

Building your yield of dreams.
IEEE Des. Test Comput., 2008

A progressive-ILP based routing algorithm for cross-referencing biochips.
Proceedings of the 45th Design Automation Conference, 2008

Reinventing EDA with manycore processors.
Proceedings of the 45th Design Automation Conference, 2008

A framework for block-based timing sensitivity analysis.
Proceedings of the 45th Design Automation Conference, 2008

2007
Simultaneous Shield and Buffer Insertion for Crosstalk Noise Reduction in Global Routing.
IEEE Trans. Very Large Scale Integr. Syst., 2007

Prediction of leakage power under process uncertainties.
ACM Trans. Design Autom. Electr. Syst., 2007

High-Efficiency Green Function-Based Thermal Simulation Algorithms.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2007

In Memoriam: Margarida F. Jacome.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2007

Editorial to special issue DAC 2006.
ACM J. Emerg. Technol. Comput. Syst., 2007

DAC Highlights.
IEEE Des. Test Comput., 2007

Book Review: An Assay of Biochips.
IEEE Des. Test Comput., 2007

Probabilistic Congestion Prediction with Partial Blockages.
Proceedings of the 8th International Symposium on Quality of Electronic Design (ISQED 2007), 2007

Module assignment for pin-limited designs under the stacked-Vdd paradigm.
Proceedings of the 2007 International Conference on Computer-Aided Design, 2007

Clustering based pruning for statistical criticality computation under process variations.
Proceedings of the 2007 International Conference on Computer-Aided Design, 2007

A general model for performance optimization of sequential systems.
Proceedings of the 2007 International Conference on Computer-Aided Design, 2007

Computer-aided design of 3d integrated circuits.
Proceedings of the 17th ACM Great Lakes Symposium on VLSI 2007, 2007

DAG based library-free technology mapping.
Proceedings of the 17th ACM Great Lakes Symposium on VLSI 2007, 2007

Confidence Scalable Post-Silicon Statistical Delay Prediction under Process Variations.
Proceedings of the 44th Design Automation Conference, 2007

NBTI-Aware Synthesis of Digital Circuits.
Proceedings of the 44th Design Automation Conference, 2007

Width-dependent Statistical Leakage Modeling for Random Dopant Induced Threshold Voltage Shift.
Proceedings of the 44th Design Automation Conference, 2007

Placement of 3D ICs with Thermal and Interlayer Via Considerations.
Proceedings of the 44th Design Automation Conference, 2007

Routing Congestion in VLSI Circuits - Estimation and Optimization.
Series on Integrated Circuits and Systems, Springer, ISBN: 978-0-387-48550-8, 2007

2006
Partition-Based Algorithm for Power Grid Design Using Locality.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2006

Technology Mapping Algorithm Targeting Routing Congestion Under Delay Constraints.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2006

Placement of Thermal Vias in 3-D ICs Using Various Thermal Objectives.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2006

Accurate estimation of global buffer delay within a floorplan.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2006

Temperature-Aware Placement for SOCs.
Proceedings of the IEEE, 2006

DAC Highlights.
IEEE Des. Test Comput., 2006

Book Reviews: Plumbing the Depths of Leakage.
IEEE Des. Test Comput., 2006

Fast disjoint transistor networks from BDDs.
Proceedings of the 19th Annual Symposium on Integrated Circuits and Systems Design, 2006

Impact of NBTI on SRAM Read Stability and Design for Reliability.
Proceedings of the 7th International Symposium on Quality of Electronic Design (ISQED 2006), 2006

Tutorial II: Variability and Its Impact on Design.
Proceedings of the 7th International Symposium on Quality of Electronic Design (ISQED 2006), 2006

Comparing simulation techniques for microarchitecture-aware floorplanning.
Proceedings of the 2006 IEEE International Symposium on Performance Analysis of Systems and Software, 2006

Temperature-aware floorplanning of microarchitecture blocks with IPC-power dependence modeling and transient analysis.
Proceedings of the 2006 International Symposium on Low Power Electronics and Design, 2006

An analytical model for negative bias temperature instability.
Proceedings of the 2006 International Conference on Computer-Aided Design, 2006

Statistical timing analysis with correlated non-gaussian parameters using independent component analysis.
Proceedings of the 43rd Design Automation Conference, 2006

Subthreshold logical effort: a systematic framework for optimal subthreshold device sizing.
Proceedings of the 43rd Design Automation Conference, 2006

Width Quantization Aware FinFET Circuit Design.
Proceedings of the IEEE 2006 Custom Integrated Circuits Conference, 2006

Temperature-aware routing in 3D ICs.
Proceedings of the 2006 Conference on Asia South Pacific Design Automation: ASP-DAC 2006, 2006

Electrothermal analysis and optimization techniques for nanoscale integrated circuits.
Proceedings of the 2006 Conference on Asia South Pacific Design Automation: ASP-DAC 2006, 2006

A fixed-die floorplanning algorithm using an analytical approach.
Proceedings of the 2006 Conference on Asia South Pacific Design Automation: ASP-DAC 2006, 2006

Mathematically assisted adaptive body bias (ABB) for temperature compensation in gigascale LSI systems.
Proceedings of the 2006 Conference on Asia South Pacific Design Automation: ASP-DAC 2006, 2006

2005
Gate oxide leakage and delay tradeoffs for dual-T/sub ox/ circuits.
IEEE Trans. Very Large Scale Integr. Syst., 2005

BDD decomposition for delay oriented pass transistor logic synthesis.
IEEE Trans. Very Large Scale Integr. Syst., 2005

Fast comparisons of circuit implementations.
IEEE Trans. Very Large Scale Integr. Syst., 2005

Congestion-aware topology optimization of structured power/ground networks.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2005

A predictive distributed congestion metric with application to technology mapping.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2005

Power grid analysis using random walks.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2005

Early-stage power grid analysis for uncertain working modes.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2005

Statistical timing analysis under spatial correlations.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2005

Guest Editors' Introduction: New Dimensions in 3D Integration.
IEEE Des. Test Comput., 2005

Designing "Vary" Good Circuitry.
IEEE Des. Test Comput., 2005

Empowering the designer.
IEEE Des. Test Comput., 2005

An EDA compendium.
IEEE Des. Test Comput., 2005

Placement and Routing in 3D Integrated Circuits.
IEEE Des. Test Comput., 2005

High-Speed Interconnect Technology: On-Chip and Off-Chip.
Proceedings of the 18th International Conference on VLSI Design (VLSI Design 2005), 2005

A fast algorithm for power grid design.
Proceedings of the 2005 International Symposium on Physical Design, 2005

An efficient technology mapping algorithm targeting routing congestion under delay constraints.
Proceedings of the 2005 International Symposium on Physical Design, 2005

Thermal via placement in 3D ICs.
Proceedings of the 2005 International Symposium on Physical Design, 2005

Designing optimized pipelined global interconnects: algorithms and methodology impact.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005

Fast estimation of area-delay trade-offs in circuit sizing.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005

Exact lower bound for the number of switches in series to implement a combinational logic cell.
Proceedings of the 23rd International Conference on Computer Design (ICCD 2005), 2005

A high efficiency full-chip thermal simulation algorithm.
Proceedings of the 2005 International Conference on Computer-Aided Design, 2005

A hybrid linear equation solver and its application in quadratic placement.
Proceedings of the 2005 International Conference on Computer-Aided Design, 2005

A new approach to the use of satisfiability in false path detection.
Proceedings of the 15th ACM Great Lakes Symposium on VLSI 2005, 2005

Robust gate sizing by geometric programming.
Proceedings of the 42nd Design Automation Conference, 2005

Microarchitecture-aware floorplanning using a statistical design of experiments approach.
Proceedings of the 42nd Design Automation Conference, 2005

Net weighting to reduce repeater counts during placement.
Proceedings of the 42nd Design Automation Conference, 2005

Full-chip analysis of leakage power under process variations, including spatial correlations.
Proceedings of the 42nd Design Automation Conference, 2005

Fast computation of the temperature distribution in VLSI chips using the discrete cosine transform and table look-up.
Proceedings of the 2005 Conference on Asia South Pacific Design Automation, 2005

2004
A new approach for integration of min-area retiming and min-delay padding for simultaneously addressing short-path and long-path constraints.
ACM Trans. Design Autom. Electr. Syst., 2004

A methodology for the simultaneous design of supply and signal networks.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2004

High-Performance Power Grids For Nanometer Technologies.
Proceedings of the 17th International Conference on VLSI Design (VLSI Design 2004), 2004

The Certainty of Uncertainty: Randomness in Nanometer Design.
Proceedings of the Integrated Circuit and System Design, 2004

Topology optimization of structured power/ground networks.
Proceedings of the 2004 International Symposium on Physical Design, 2004

A predictive distributed congestion metric and its application to technology mapping.
Proceedings of the 2004 International Symposium on Physical Design, 2004

Transistor and Pin Reordering for Gate Oxide Leakage Reduction in Dual T{ox} Circuits.
Proceedings of the 22nd IEEE International Conference on Computer Design: VLSI in Computers & Processors (ICCD 2004), 2004

A chip-level electrostatic discharge simulation strategy.
Proceedings of the 2004 International Conference on Computer-Aided Design, 2004

Logical effort based technology mapping.
Proceedings of the 2004 International Conference on Computer-Aided Design, 2004

Optimization of Integrated Spiral Inductors Using Sequential Quadratic Programming.
Proceedings of the 2004 Design, 2004

Tradeoffs between date oxide leakage and delay for dual T<sub>ox</sub> circuits.
Proceedings of the 41th Design Automation Conference, 2004

A method for correcting the functionality of a wire-pipelined circuit.
Proceedings of the 41th Design Automation Conference, 2004

On the selection of on-chip inductors for the optimal VCO design.
Proceedings of the IEEE 2004 Custom Integrated Circuits Conference, 2004

Hierarchical random-walk algorithms for power grid analysis.
Proceedings of the 2004 Conference on Asia South Pacific Design Automation: Electronic Design and Solution Fair 2004, 2004

Timing.
Kluwer, ISBN: 978-1-4020-7671-8, 2004

2003
Technology mapping for SOI domino logic incorporating solutions for the parasitic bipolar effect.
IEEE Trans. Very Large Scale Integr. Syst., 2003

Optimal decoupling capacitor sizing and placement for standard-cell layout designs.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2003

Analysis and optimization of structured power/ground networks.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2003

Fast on-chip inductance simulation using a precorrected-FFT method.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2003

Guest editorial.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2003

A practical methodology for early buffer and wire resource allocation.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2003

Analysis and Optimization of Power Grids.
IEEE Des. Test Comput., 2003

Partition-driven standard cell thermal placement.
Proceedings of the 2003 International Symposium on Physical Design, 2003

Table look-up based compact modeling for on-chip interconnect timing and noise analysis.
Proceedings of the 2003 International Symposium on Circuits and Systems, 2003

An Efficient Algorithm for Calculating the Worst-case Delay due to Crosstalk.
Proceedings of the 21st International Conference on Computer Design (ICCD 2003), 2003

Efficient Thermal Placement of Standard Cells in 3D ICs using a Force Directed Approach.
Proceedings of the 2003 International Conference on Computer-Aided Design, 2003

Statistical Timing Analysis Considering Spatial Correlations using a Single Pert-Like Traversal.
Proceedings of the 2003 International Conference on Computer-Aided Design, 2003

Random walks in a supply network.
Proceedings of the 40th Design Automation Conference, 2003

2002
Performance Driven Global Routing Through Gradual Refinement.
VLSI Design, 2002

Low-power clock distribution using multiple voltages and reduced swings.
IEEE Trans. Very Large Scale Integr. Syst., 2002

Efficient inductance extraction using circuit-aware techniques.
IEEE Trans. Very Large Scale Integr. Syst., 2002

Technology mapping algorithms for domino logic.
ACM Trans. Design Autom. Electr. Syst., 2002

Hierarchical analysis of power distribution networks.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2002

Fast and exact transistor sizing based on iterative relaxation.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2002

A timing-constrained simultaneous global routing algorithm.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2002

Probability-driven routing in a datapath environment.
Integr., 2002

An Efficient Algorithm for Low Power Pass Transistor Logic Synthesis.
Proceedings of the ASPDAC 2002 / VLSI Design 2002, 2002

Optimized pin assignment for lower routing congestion after floorplanning phase.
Proceedings of the Fourth IEEE/ACM International Workshop on System-Level Interconnect Prediction (SLIP 2002), 2002

Efficient Layout Synthesis Algorithm for Pass Transistor Logic Circuits.
Proceedings of the 11th IEEE/ACM International Workshop on Logic & Synthesis, 2002

An algorithm for optimal decoupling capacitor sizing and placement for standard cell layouts.
Proceedings of 2002 International Symposium on Physical Design, 2002

Efficient PEEC-Based Inductance Extraction Using Circuit-Aware Techniques.
Proceedings of the 20th International Conference on Computer Design (ICCD 2002), 2002

Standby power optimization via transistor sizing and dual threshold voltage assignment.
Proceedings of the 2002 IEEE/ACM International Conference on Computer-aided Design, 2002

A precorrected-FFT method for simulating on-chip inductance.
Proceedings of the 2002 IEEE/ACM International Conference on Computer-aided Design, 2002

Congestion-driven codesign of power and signal networks.
Proceedings of the 39th Design Automation Conference, 2002

2001
Technology mapping for high-performance static CMOS and pass transistor logic designs.
IEEE Trans. Very Large Scale Integr. Syst., 2001

Exact and efficient crosstalk estimation.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2001

Steiner tree optimization for buffers, blockages, and bays.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2001

A survey on multi-net global routing for integrated circuits.
Integr., 2001

Optimization and Analysis Techniques for the Deep Submicron Regime.
Proceedings of the 14th International Conference on VLSI Design (VLSI Design 2001), 2001

Buffered Steiner trees for difficult instances.
Proceedings of the 2001 International Symposium on Physical Design, 2001

Hybrid Structured Clock Network Construction.
Proceedings of the 2001 IEEE/ACM International Conference on Computer-Aided Design, 2001

Recursive Bipartitioning of BDDs for Performance Driven Synthesis of Pass Transistor Logic Circuits.
Proceedings of the 2001 IEEE/ACM International Conference on Computer-Aided Design, 2001

A New Structural Pattern Matching Algorithm for Technology Mapping.
Proceedings of the 38th Design Automation Conference, 2001

2000
Power-delay optimizations in gate sizing.
ACM Trans. Design Autom. Electr. Syst., 2000

Timing-driven partitioning and timing optimization of mixedstatic-domino implementations.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2000

A timing model incorporating the effect of crosstalk on delay andits application to optimal channel routing.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2000

A new class of convex functions for delay modeling and itsapplication to the transistor sizing problem [CMOS gates].
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2000

Algorithms for non-Hanan-based optimization for VLSI interconnectunder a higher-order AWE model.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2000

Capturing the Effect of Crosstalk on Delay.
Proceedings of the 13th International Conference on VLSI Design (VLSI Design 2000), 2000

Datapath routing based on a decongestion metric.
Proceedings of the 2000 International Symposium on Physical Design, 2000

Dual-monotonic domino gate mapping and optimal output phase assignment of domino logic.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2000

Fast Analysis and Optimization of Power/Ground Networks.
Proceedings of the 2000 IEEE/ACM International Conference on Computer-Aided Design, 2000

A Timing-Constrained Algorithm for Simultaneous Global Routing of Multiple Nets.
Proceedings of the 2000 IEEE/ACM International Conference on Computer-Aided Design, 2000

Hierarchical analysis of power distribution networks.
Proceedings of the 37th Conference on Design Automation, 2000

MINFLOTRANSIT: min-cost flow based transistor sizing tool.
Proceedings of the 37th Conference on Design Automation, 2000

Convex delay models for transistor sizing.
Proceedings of the 37th Conference on Design Automation, 2000

1999
Optimizing large multiphase level-clocked circuits.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1999

Non-Hanan routing.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1999

Retiming control logic.
Integr., 1999

Simultaneous buffer insertion and non-Hanan optimization for VLSI interconnect under a higher order AWE model.
Proceedings of the 1999 International Symposium on Physical Design, 1999

Clock distribution using multiple voltages.
Proceedings of the 1999 International Symposium on Low Power Electronics and Design, 1999

Efficient Crosstalk Estimation.
Proceedings of the IEEE International Conference On Computer Design, 1999

Timing-driven partitioning for two-phase domino and mixed static/domino implementations.
Proceedings of the 1999 IEEE/ACM International Conference on Computer-Aided Design, 1999

Marsh: min-area retiming with setup and hold constraints.
Proceedings of the 1999 IEEE/ACM International Conference on Computer-Aided Design, 1999

An integrated algorithm for combined placement and libraryless technology mapping.
Proceedings of the 1999 IEEE/ACM International Conference on Computer-Aided Design, 1999

FAR-DS: Full-Plane AWE Routing with Driver Sizing.
Proceedings of the 36th Conference on Design Automation, 1999

1998
Efficient retiming of large circuits.
IEEE Trans. Very Large Scale Integr. Syst., 1998

Interleaving buffer insertion and transistor sizing into a single optimization.
IEEE Trans. Very Large Scale Integr. Syst., 1998

Speeding up pipelined circuits through a combination of gate sizing and clock skew optimization.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1998

Routing tree topology construction to meet interconnect timing constraints.
Proceedings of the 1998 International Symposium on Physical Design, 1998

A fast global gate collapsing technique for high performance designs using static CMOS and pass transistor logic.
Proceedings of the International Conference on Computer Design: VLSI in Computers and Processors, 1998

Technology mapping for domino logic.
Proceedings of the 1998 IEEE/ACM International Conference on Computer-Aided Design, 1998

Efficient Minarea Retiming of Large Level-Clocked Circuits.
Proceedings of the 1998 Design, 1998

1997
A Framework for Exploiting Task and Data Parallelism on Distributed Memory Multicomputers.
IEEE Trans. Parallel Distrib. Syst., 1997

Concurrent transistor sizing and buffer insertion by considering cost-delay tradeoffs.
Proceedings of the 1997 International Symposium on Physical Design, 1997

Minimum area retiming with equivalent initial states.
Proceedings of the 1997 IEEE/ACM International Conference on Computer-Aided Design, 1997

An Improved Algorithm for Minimum-Area Retiming.
Proceedings of the 34st Conference on Design Automation, 1997

1996
Utilizing the retiming-skew equivalence in a practical algorithm for retiming large circuits.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1996

Wire sizing as a convex optimization problem: exploring the area-delay tradeoff.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1996

Optimal design of macrocells for low power and high speed.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1996

Wiresizing with Buffer Placement and Sizing for Power-Delay Tradeoffs.
Proceedings of the 9th International Conference on VLSI Design (VLSI Design 1996), 1996

A Practical Algorithm for Retiming Level-Clocked Circuits.
Proceedings of the 1996 International Conference on Computer Design (ICCD '96), 1996

Clock tree synthesis for multi-chip modules.
Proceedings of the 1996 IEEE/ACM International Conference on Computer-Aided Design, 1996

1995
Timing and area optimization for standard-cell VLSI circuit design.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1995

Layout Optimization Using Arbitrarily High Degree Posynomial Models.
Proceedings of the 1995 IEEE International Symposium on Circuits and Systems, ISCAS 1995, Seattle, Washington, USA, April 30, 1995

Power vs. delay in gate sizing: conflicting objectives?
Proceedings of the 1995 IEEE/ACM International Conference on Computer-Aided Design, 1995

A Fresh Look at Retiming Via Clock Skew Optimization.
Proceedings of the 32st Conference on Design Automation, 1995

1994
Convexity-based algorithms for design centering.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1994

High Performance CMOS Macromodule Layout Synthesis.
Proceedings of the 1994 IEEE International Symposium on Circuits and Systems, ISCAS 1994, London, England, UK, May 30, 1994

A Graph-Theoretic Approach to Clock Skew Optimization.
Proceedings of the 1994 IEEE International Symposium on Circuits and Systems, ISCAS 1994, London, England, UK, May 30, 1994

A Convex Programming Approach for Exploiting Data and Functional Parallelism on Distributed Memory Multicomputers.
Proceedings of the 1994 International Conference on Parallel Processing, 1994

RC Interconnect Optimization Under the Elmore Delay Model.
Proceedings of the 31st Conference on Design Automation, 1994

1993
An exact solution to the transistor sizing problem for CMOS circuits using convex optimization.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1993

Feasible Region Approximation Using Convex Polytopes.
Proceedings of the 1993 IEEE International Symposium on Circuits and Systems, 1993

Convexity-based algorithms for design centering.
Proceedings of the 1993 IEEE/ACM International Conference on Computer-Aided Design, 1993

A unified algorithm for gate sizing and clock skew optimization to minimize sequential circuit area.
Proceedings of the 1993 IEEE/ACM International Conference on Computer-Aided Design, 1993

1991
A Convex Optimization Approach to Transistor Sizing for CMOS Circuits.
Proceedings of the 1991 IEEE/ACM International Conference on Computer-Aided Design, 1991


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