Navaneeth Rameshan

According to our database1, Navaneeth Rameshan authored at least 14 papers between 2009 and 2019.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

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In proceedings 
Article 
PhD thesis 
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Links

On csauthors.net:

Bibliography

2019
Chisel: Reshaping Queries to Trim Latency in Key-Value Stores.
Proceedings of the 2019 IEEE International Conference on Autonomic Computing, 2019

2016
On the role of performance interference in consolidated environments.
PhD thesis, 2016

Elastic Scaling in the Cloud: A Multi-tenant Perspective.
Proceedings of the 36th IEEE International Conference on Distributed Computing Systems Workshops, 2016

Augmenting Elasticity Controllers for Improved Accuracy.
Proceedings of the 2016 IEEE International Conference on Autonomic Computing, 2016

Profiling Memory Vulnerability of Big-Data Applications.
Proceedings of the 46th Annual IEEE/IFIP International Conference on Dependable Systems and Networks Workshops, 2016

Hubbub-Scale: Towards Reliable Elastic Scaling under Multi-tenancy.
Proceedings of the IEEE/ACM 16th International Symposium on Cluster, 2016

2015
ProRenaTa: Proactive and Reactive Tuning to Scale a Distributed Storage System.
Proceedings of the 15th IEEE/ACM International Symposium on Cluster, 2015

2014
<i>Stay-Away</i>, protecting sensitive applications from performance interference.
Proceedings of the 15th International Middleware Conference, 2014

Energy Efficiency Dilemma: P2P-cloud vs. Datacenter.
Proceedings of the IEEE 6th International Conference on Cloud Computing Technology and Science, 2014

2013
A monitoring system for community-lab.
Proceedings of the MobiWac'13, 2013

Resource-Aware Scaling of Multi-threaded Java Applications in Multi-tenancy Scenarios.
Proceedings of the IEEE 5th International Conference on Cloud Computing Technology and Science, 2013

2011
Acceleration of Functional Validation Using GPGPU.
Proceedings of the Sixth IEEE International Symposium on Electronic Design, 2011

2010
Minimal Path, Fault Tolerant, QoS Aware Routing with Node and Link Failure in 2-D Mesh NoC.
Proceedings of the 25th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, 2010

2009
Implementation of QoS Aware Q-Routing Algorithm for Network-on-Chip.
Proceedings of the Contemporary Computing - Second International Conference, 2009


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