Mark Zwolinski

Orcid: 0000-0002-2230-625X

Affiliations:
  • University of Southampton, School of Electronics and Computer Science, UK


According to our database1, Mark Zwolinski authored at least 129 papers between 1990 and 2024.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

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Online presence:

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Bibliography

2024
SEA Cache: A Performance-Efficient Countermeasure for Contention-based Attacks.
CoRR, 2024

Using Formal Verification to Evaluate Single Event Upsets in a RISC-V Core.
CoRR, 2024

2022
Using Formal Methods to Evaluate Hardware Reliability in the Presence of Soft Errors.
Proceedings of the 17th Conference on Ph.D Research in Microelectronics and Electronics, 2022

Mitigating Cache Contention-Based Attacks by Logical Associativity.
Proceedings of the 17th Conference on Ph.D Research in Microelectronics and Electronics, 2022

Session details: Session 4A: Testing, Reliability and Fault Tolerance.
Proceedings of the GLSVLSI '22: Great Lakes Symposium on VLSI 2022, Irvine CA USA, June 6, 2022

2021
Learning-based BTI stress estimation and mitigation in multi-core processor systems.
Microprocess. Microsystems, 2021

A Survey on the Susceptibility of PUFs to Invasive, Semi-Invasive and Noninvasive Attacks: Challenges and Opportunities for Future Directions.
J. Circuits Syst. Comput., 2021

2019
Editorial TVLSI Positioning - Continuing and Accelerating an Upward Trajectory.
IEEE Trans. Very Large Scale Integr. Syst., 2019

A reliable PUF in a dual function SRAM.
Integr., 2019

VLSI Implementation of a Fully-Pipelined K-Best MIMO Detector with Successive Interference Cancellation.
Circuits Syst. Signal Process., 2019

Using Hardware Performance Counters to Detect Control Hijacking Attacks.
Proceedings of the 4th IEEE International Verification and Security Workshop, 2019

Two-Stage Architectures for Resilient Lightweight PUFs.
Proceedings of the 4th IEEE International Verification and Security Workshop, 2019

2018
Lifetime Reliability-Aware Digital Synthesis.
IEEE Trans. Very Large Scale Integr. Syst., 2018

Multi-Path Aging Sensor for Cost-Efficient Delay Fault Prediction.
IEEE Trans. Circuits Syst. II Express Briefs, 2018

Hardware Implementation of a Low-Power K-Best MIMO Detector Based on a Hybrid Merge Network.
Proceedings of the 28th International Symposium on Power and Timing Modeling, 2018

A Machine Learning Attacks Resistant Two Stage Physical Unclonable Functions Design.
Proceedings of the 3rd IEEE International Verification and Security Workshop, 2018

A Power Efficient Crossbar Arbitration in Multi-NoC for Multicast and Broadcast Traffic.
Proceedings of the IEEE International Symposium on Smart Electronic Systems, 2018

Early detection of system-level anomalous behaviour using hardware performance counters.
Proceedings of the 2018 Design, Automation & Test in Europe Conference & Exhibition, 2018

Cost-efficient design for modeling attacks resistant PUFs.
Proceedings of the 2018 Design, Automation & Test in Europe Conference & Exhibition, 2018

Cell Flipping with Distributed Refresh for Cache Ageing Minimization.
Proceedings of the 27th IEEE Asian Test Symposium, 2018

2017
BTI mitigation by anti-ageing software patterns.
Microelectron. Reliab., 2017

An ageing-aware digital synthesis approach.
Proceedings of the 14th International Conference on Synthesis, 2017

Lightweight obfuscation techniques for modeling attacks resistant PUFs.
Proceedings of the IEEE 2nd International Verification and Security Workshop, 2017

Hardware performance counters for system reliability monitoring.
Proceedings of the IEEE 2nd International Verification and Security Workshop, 2017

A cost-efficient delay-fault monitor.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2017

Fault analysis in analog circuits through language manipulation and abstraction.
Proceedings of the 2017 Forum on Specification and Design Languages, 2017

2016
A Low-Cost, Radiation-Hardened Method for Pipeline Protection in Microprocessors.
IEEE Trans. Very Large Scale Integr. Syst., 2016

Resilient routing implementation in 2D mesh NoC.
Microelectron. Reliab., 2016

Guest Editorial.
IET Comput. Digit. Tech., 2016

<i>σ</i> <sup> <i>n</i> </sup>LBDR: generic congestion handling routing implementation for two-dimensional mesh network-on-chip.
IET Comput. Digit. Tech., 2016

A Survey of VLSI Implementations of Tree Search Algorithms for MIMO Detection.
Circuits Syst. Signal Process., 2016

IEEE Access Special Section Editorial: Security and Reliability Aware System Design for Mobile Computing Devices.
IEEE Access, 2016

Using Iddt current degradation to monitor ageing in CMOS circuits.
Proceedings of the 26th International Workshop on Power and Timing Modeling, 2016

Overview of PUF-based hardware security solutions for the internet of things.
Proceedings of the IEEE 59th International Midwest Symposium on Circuits and Systems, 2016

NBTI aging evaluation of PUF-based differential architectures.
Proceedings of the 22nd IEEE International Symposium on On-Line Testing and Robust System Design, 2016

High accuracy implementation of Adaptive Exponential integrated and fire neuron model.
Proceedings of the 2016 International Joint Conference on Neural Networks, 2016

The European Masters in Embedded Computing Systems (EMECS).
Proceedings of the 11th European Workshop on Microelectronics Education, 2016

The influence of hysteresis voltage on single event transients in a 65nm CMOS high speed comparator.
Proceedings of the 21th IEEE European Test Symposium, 2016

Ageing Impact on a High Speed Voltage Comparator with Hysteresis.
Proceedings of the Workshop on Early Reliability Modeling for Aging and Variability in Silicon Systems, 2016

NBTI Lifetime Evaluation and Extension in Instruction Caches.
Proceedings of the Workshop on Early Reliability Modeling for Aging and Variability in Silicon Systems, 2016

Static Aging Analysis Using 3-Dimensional Delay Library.
Proceedings of the Workshop on Early Reliability Modeling for Aging and Variability in Silicon Systems, 2016

2015
Resistive Open Faults Detectability Analysis and Implications for Testing Low Power Nanometric ICs.
IEEE Trans. Very Large Scale Integr. Syst., 2015

Parallel Sparse Matrix Solution for Circuit Simulation on FPGAs.
IEEE Trans. Computers, 2015

Implications of Burn-In Stress on NBTI Degradation.
CoRR, 2015

Fault Tolerance in Distributed Neural Computing.
CoRR, 2015

In-Field Logic Repair of Deep Sub-Micron CMOS Processors.
CoRR, 2015

CERI: Cost-Effective Routing Implementation Technique for Network-on-Chip.
Proceedings of the 28th International Conference on VLSI Design, 2015

A framework for thermal aware reliability estimation in 2D NoC.
Proceedings of the 19th International Symposium on VLSI Design and Test, 2015

σLBDR: Congestion-aware logic based distributed routing for 2D NoC.
Proceedings of the 19th International Symposium on VLSI Design and Test, 2015

Network-on-chip: Current issues and challenges.
Proceedings of the 19th International Symposium on VLSI Design and Test, 2015

VLSI implementation of a scalable K-best MIMO detector.
Proceedings of the 15th International Symposium on Communications and Information Technologies, 2015

Conservative behavioural modelling in systemc-AMS.
Proceedings of the 2015 Forum on Specification and Design Languages, 2015

2014
Multivoltage Aware Resistive Open Fault Model.
IEEE Trans. Very Large Scale Integr. Syst., 2014

Monte Carlo Static Timing Analysis with statistical sampling.
Microelectron. Reliab., 2014

CARM: Congestion Adaptive Routing Method for On Chip Networks.
Proceedings of the 2014 27th International Conference on VLSI Design, 2014

A novel non-minimal turn model for highly adaptive routing in 2D NoCs.
Proceedings of the 22nd International Conference on Very Large Scale Integration, 2014

Fault tolerant routing implementation mechanism for irregular 2D mesh NoCs.
Proceedings of the 2014 NORCHIP, Tampere, Finland, October 27-28, 2014, 2014

A novel non-minimal/minimal turn model for highly adaptive routing in 2D NoCs.
Proceedings of the Eighth IEEE/ACM International Symposium on Networks-on-Chip, 2014

A cost-efficient self-checking register architecture for radiation hardened designs.
Proceedings of the IEEE International Symposium on Circuits and Systemss, 2014

Highly adaptive and congestion-aware routing for 3D NoCs.
Proceedings of the Great Lakes Symposium on VLSI 2014, GLSVLSI '14, Houston, TX, USA - May 21, 2014

Fault tolerant and highly adaptive routing for 2D NoCs.
Proceedings of the 2014 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2014

Efficient simulation and modelling of non-rectangular NoC topologies.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2014

A low-cost radiation hardened flip-flop.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2014

2013
Energy-Conscious Turbo Decoder Design: A Joint Signal Processing and Transmit Energy Reduction Approach.
IEEE Trans. Veh. Technol., 2013

Oscillation-based analog diagnosis using artificial neural networks based inference mechanism.
Comput. Electr. Eng., 2013

Circuit Transient Analysis Using State Space Equations.
Proceedings of the VLSI Design and Test, 17th International Symposium, 2013

ISPD 2013 expert designer/user session (eds).
Proceedings of the International Symposium on Physical Design, 2013

2012
A Large Scale Digital Simulation of Spiking Neural Networks (SNN) on Fast SystemC Simulator.
Proceedings of the 14th International Conference on Computer Modelling and Simulation, 2012

SETTOFF: A fault tolerant flip-flop for building Cost-efficient Reliable Systems.
Proceedings of the 18th IEEE International On-Line Testing Symposium, 2012

2011
On the VLSI Implementation of Adaptive-Frequency Hopf Oscillator.
IEEE Trans. Circuits Syst. I Regul. Pap., 2011

Fixed-point multiplication: A probabilistic bit-pattern view.
Microelectron. Reliab., 2011

Acceleration of packet filtering using gpgpu.
Proceedings of the 4th International Conference on Security of Information and Networks, 2011

Parallelizing TUNAMI-N1 Using GPGPU.
Proceedings of the 13th IEEE International Conference on High Performance Computing & Communication, 2011

Timing Vulnerability Factors of Ultra Deep-sub-micron CMOS.
Proceedings of the 16th European Test Symposium, 2011

Acceleration of Functional Validation Using GPGPU.
Proceedings of the Sixth IEEE International Symposium on Electronic Design, 2011

Modelling circuit performance variations due to statistical variability: Monte Carlo static timing analysis.
Proceedings of the Design, Automation and Test in Europe, 2011

Radiation hardening by design: A novel gate level approach.
Proceedings of the 2011 NASA/ESA Conference on Adaptive Hardware and Systems, 2011

2010
Very large scale integration architecture for integer wavelet transform.
IET Comput. Digit. Tech., 2010

Parallel sparse matrix solver for direct circuit simulations on FPGAs.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2010), May 30, 2010

Design metrics for RTL level estimation of delay variability due to intradie (random) variations.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2010), May 30, 2010

Modelling Smart Card Security Protocols in SystemC TLM.
Proceedings of the IEEE/IFIP 8th International Conference on Embedded and Ubiquitous Computing, 2010

A communication infrastructure for a million processor machine.
Proceedings of the 7th Conference on Computing Frontiers, 2010

2009
New concepts of worst-case delay and yield estimation in asynchronous VLSI circuits.
Microelectron. Reliab., 2009

Analytical Transient Response and Propagation Delay Model for Nanoscale CMOS Inverter.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2009), 2009

Variation resilient adaptive controller for subthreshold circuits.
Proceedings of the Design, Automation and Test in Europe, 2009

2008
Path switching: a technique to tolerate dual rail routing imbalances.
Des. Autom. Embed. Syst., 2008

On the probability distribution of fixed-point multiplication.
Proceedings of the 15th IEEE International Conference on Electronics, Circuits and Systems, 2008

Symbolic noise analysis approach to computational hardware optimization.
Proceedings of the 45th Design Automation Conference, 2008

Divided Backend Duplication Methodology for Balanced Dual Rail Routing.
Proceedings of the Cryptographic Hardware and Embedded Systems, 2008

Behavioural Modelling for Stability of CMOS SRAM Cells Subject to Random Discrete Doping.
Proceedings of the 2008 IEEE International Behavioral Modeling and Simulation Workshop, 2008

2007
Using neural networks as a fault detection mechanism in MEMS devices.
Microelectron. Reliab., 2007

Evaluation of Dynamic Voltage and Frequency Scaling as a Differential Power Analysis Countermeasure.
Proceedings of the 20th International Conference on VLSI Design (VLSI Design 2007), 2007

Multiple-Width Bus Partitioning Approach to Datapath Synthesis.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2007), 2007

General and Technical Program Chairs' Message.
Proceedings of the 14th IEEE International Conference on Electronics, 2007

Testing of Level Shifters in Multiple Voltage Designs.
Proceedings of the 14th IEEE International Conference on Electronics, 2007

A novel self-routing reconfigurable fault-tolerant cell array.
Proceedings of the Second NASA/ESA Conference on Adaptive Hardware and Systems (AHS 2007), 2007

2006
An Integrated High-Level On-Line Test Synthesis Tool.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2006

On the Design of Self-Checking Controllers with Datapath Interactions.
IEEE Trans. Computers, 2006

Analogue electronic circuit diagnosis based on ANNs.
Microelectron. Reliab., 2006

Reversible Logic to Cryptographic Hardware: A New Paradigm
CoRR, 2006

Dynamic Voltage Scaling Aware Delay Fault Testing.
Proceedings of the 11th European Test Symposium, 2006

2005
Behavioural modelling, simulation, test and diagnosis of MEMS using ANNs.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005

2004
Concurrent analogue fault simulation, the equation formulation aspect.
Int. J. Circuit Theory Appl., 2004

Generation and Verification of Tests for Analog Circuits Subject to Process Parameter Deviations.
J. Electron. Test., 2004

Integrating Self Testability with Design Space Exploration by a Controller based Estimation Technique.
Proceedings of the 17th International Conference on VLSI Design (VLSI Design 2004), 2004

Behavioural modelling of analogue faults in VHDL-AMS - a case study.
Proceedings of the 2004 International Symposium on Circuits and Systems, 2004

2003
Globally convergent algorithms for DC operating point analysis of nonlinear circuits.
IEEE Trans. Evol. Comput., 2003

Integrating testability with design space exploration.
Microelectron. Reliab., 2003

The continuous-discrete interface - What does this really mean? Modelling and simulation issues.
Proceedings of the 2003 International Symposium on Circuits and Systems, 2003

Foundation of Combined Datapath and Controller Self-checking Design.
Proceedings of the 9th IEEE International On-Line Testing Symposium (IOLTS 2003), 2003

Versatile High-Level Synthesis of Self-Checking Datapaths Using an On-Line Testability Metric.
Proceedings of the 2003 Design, 2003

2002
Transformation Based Insertion of On-Line Testing Resources in a High-Level Synthesis Environment.
Proceedings of the 8th IEEE International On-Line Testing Workshop (IOLTW 2002), 2002

Behavioural Modelling of Operational Amplifier Faults Using VHDL-AMS.
Proceedings of the 2002 Design, 2002

Using evolutionary and hybrid algorithms for DC operating point analysis of nonlinear circuits.
Proceedings of the 2002 Congress on Evolutionary Computation, 2002

2001
Mutual Information Theory for Adaptive Mixture Models.
IEEE Trans. Pattern Anal. Mach. Intell., 2001

A technique for transparent fault injection and simulation in VHDL.
Microelectron. Reliab., 2001

Practical algorithms for fully decoupled mixed-mode simulation of electronic circuits.
Proceedings of the 2001 International Symposium on Circuits and Systems, 2001

Process variation independent built-in current sensor for analogue built-in self-test.
Proceedings of the 2001 International Symposium on Circuits and Systems, 2001

2000
Applying a robust heteroscedastic probabilistic neural network toanalog fault detection and classification.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2000

Applying Mutual Information to Adaptive Mixture Models.
Proceedings of the Intelligent Data Engineering and Automated Learning, 2000

1999
Fast, Robust DC and Transient Fault Simulation for Nonlinear Analog Circuits.
Proceedings of the 1999 Design, 1999

Testing analog circuits by supply voltage variation and supply current monitoring.
Proceedings of the IEEE 1999 Custom Integrated Circuits Conference, 1999

1998
A design for test technique to increase the resolution of analogue supply current tests.
Proceedings of the 5th IEEE International Conference on Electronics, Circuits and Systems, 1998

1997
Generation and Verification of Tests for Analogue Circuits Subject to Process Parameter Deviations.
Proceedings of the 1997 Workshop on Defect and Fault-Tolerance in VLSI Systems (DFT '97), 1997

1996
Analogue Fault Modelling and Simulation for Supply Current Monitoring.
Proceedings of the 1996 European Design and Test Conference, 1996

1992
Confidence in mixed-mode circuit simulation.
Comput. Aided Des., 1992

Interleaving: an additional topological compaction technique for Weinberger array generation.
Comput. Aided Des., 1992

1991
A General Purpose Network Solving System.
Proceedings of the VLSI 91, 1991

1990
Lee router modified for global routing.
Comput. Aided Des., 1990


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