Naveen John

According to our database, Naveen John authored at least 5 papers between 2018 and 2021.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2021

Provably Secure Data Sharing Approach for Personal Health Records in Cloud Storage Using Session Password, Data Access Key, and Circular Interpolation.

Naveen John, I. Shatheesh Sam

Int. J. Semantic Web Inf. Syst., 2021

2019

An All-Digital Fused PLL-Buck Architecture for 82% Average V_dd-Margin Reduction in a 0.6-to-1.0-V Cortex-M0 Processor.

Xun Sun, Fahim ur Rahman, Venkata Rajesh Pamula, Sung Kim, Xi Li, Naveen John, Visvesh S. Sathe

IEEE J. Solid State Circuits, 2019

A Unified Clock and Switched-Capacitor-Based Power Delivery Architecture for Variation Tolerance in Low-Voltage SoC Domains.

Fahim ur Rahman, Sung Kim, Naveen John, Roshan Kumar, Xi Li, Rajesh Pamula, Keith A. Bowman, Visvesh S. Sathe

IEEE J. Solid State Circuits, 2019

2018

An All-Digital Unified Clock Frequency and Switched-Capacitor Voltage Regulator for Variation Tolerance in a Sub-Threshold ARM Cortex M0 Processor.

Fahim ur Rahman, Sung Kim, Naveen John, Roshan Kumar, Xi Li, Rajesh Pamula, Keith A. Bowman, Visvesh S. Sathe

Proceedings of the 2018 IEEE Symposium on VLSI Circuits, 2018

A combined all-digital PLL-buck slack regulation system with autonomous CCM/DCM transition control and 82% average voltage-margin reduction in a 0.6-to-1.0V cortex-M0 processor.

Xun Sun, Sung Kim, Fahim ur Rahman, Venkata Rajesh Pamula, Xi Li, Naveen John, Visvesh S. Sathe

Proceedings of the 2018 IEEE International Solid-State Circuits Conference, 2018