Navneet Kaur Saini

Orcid: 0000-0003-0127-7565

According to our database1, Navneet Kaur Saini authored at least 2 papers between 2016 and 2025.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of five.

Timeline

Legend:

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PhD thesis 
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Links

On csauthors.net:

Bibliography

2025
Drain side pocket-based Germanium nanotube tunnel FET for low power complementary ternary inverter.
Microelectron. J., 2025

2016
Low power circuit techniques for optimizing power in high speed SRAMs.
Proceedings of the 2016 International Conference on Advances in Computing, 2016


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