Nejmeddine Bahri

Orcid: 0000-0003-1821-8430

According to our database1, Nejmeddine Bahri authored at least 11 papers between 2013 and 2020.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
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Links

Online presence:

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Bibliography

2020
Optimised HEVC encoder intra-only configuration.
IET Comput. Digit. Tech., 2020

2019
Parallel implementation of HEVC encoder on multicore ARM-based platform.
Proceedings of the 16th International Multi-Conference on Systems, Signals & Devices, 2019

2018
Optimisation of HEVC motion estimation exploiting SAD and SSD GPU-based implementation.
IET Image Process., 2018

2017
Embedded Real-Time H264/AVC High Definition Video Encoder on TI's KeyStone Multicore DSP.
J. Signal Process. Syst., 2017

2016
Real-time H264/AVC encoder based on enhanced frame level parallelism for smart multicore DSP camera.
J. Real Time Image Process., 2016

SAD and SSE implementation for HEVC encoder on DSP TMS320C6678.
Proceedings of the International Image Processing, Applications and Systems, 2016

Fast motion estimation for HEVC video coding.
Proceedings of the International Image Processing, Applications and Systems, 2016

2015
Étude et conception d'un encodeur vidéo H264/AVC de résolution HD sur une plateforme multicœur. (Study and design of an H264/AVC high-definition video encoder on multicore platform).
PhD thesis, 2015

H.264/AVC high definition intra coding implementation on multiprocessor system on chip technology architecture.
IET Comput. Digit. Tech., 2015

2014
DSP-based down-sampling process using lanczos filter bank.
Proceedings of the 2014 1st International Conference on Advanced Technologies for Signal and Image Processing (ATSIP), 2014

2013
Data level parallelism for H264/AVC baseline intra-prediction chain on MPSoC.
Proceedings of the 10th International Multi-Conferences on Systems, Signals & Devices, 2013


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