Thierry Grandpierre

According to our database1, Thierry Grandpierre authored at least 21 papers between 1999 and 2019.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.



In proceedings 
PhD thesis 




A New Mapping Methodology for Coarse-Grained Programmable Systolic Architectures.
Proceedings of the 22nd International Workshop on Software and Compilers for Embedded Systems, 2019

An hypervisor approach for mixed critical real-time UAV applications.
Proceedings of the IEEE International Conference on Pervasive Computing and Communications Workshops, 2019

Embedded Real-Time H264/AVC High Definition Video Encoder on TI's KeyStone Multicore DSP.
Signal Processing Systems, 2017

Real-time H264/AVC encoder based on enhanced frame level parallelism for smart multicore DSP camera.
J. Real-Time Image Processing, 2016

GPU implementation of linear morphological openings with arbitrary angle.
J. Real-Time Image Processing, 2015

Automatic Hardware/Software interface generation for SynDEx-mixte.
Proceedings of the 2014 1st International Conference on Advanced Technologies for Signal and Image Processing (ATSIP), 2014

Real-time H.264/AVC baseline decoder implementation on TMS320C6416.
J. Real-Time Image Processing, 2012

Real-time dynamic tone-mapping operator on GPU.
J. Real-Time Image Processing, 2012

Implementation of an LVQ neural network with a variable size: algorithmic specification, architectural exploration and optimized implementation on FPGA devices.
Neural Computing and Applications, 2010

Latency and power optimization in AAA methodology for integrated circuits.
Proceedings of the 17th IEEE International Conference on Electronics, 2010

Parallel Algorithm for Concurrent Computation of Connected Component Tree.
Proceedings of the Advanced Concepts for Intelligent Vision Systems, 2008

Implementing Real-Time Algorithms by using the AAA Prototyping Methodology.
Proceedings of the Embedded System Design: Topics, Techniques and Trends, IFIP TC10 Working Conference: International Embedded Systems Symposium (IESS), May 30, 2007

FPGA-based architecture for hardware compression/decompression of wide format images.
J. Real-Time Image Processing, 2006

A rapid prototyping methodology to implement and optimize image processing algorithms for FPGAs.
Proceedings of the Real-Time Image Processing 2006, San Jose, CA, USA, January 15, 2006, 2006

A Methodology to Implement Real-Time Applications onto Reconfigurable Circuits.
The Journal of Supercomputing, 2004

AAA and SynDEx-Ic: A Methodology and a Software Framework for the Implementation of Real-Time Applications onto Reconfigurable Circuits.
Proceedings of the Field Programmable Logic and Application, 2004

From Algorithm and Architecture Specifications to Automatic Generation of Distributed Real-Time Executives: a Seamless Flow of Graphs Transformations.
Proceedings of the 1st ACM & IEEE International Conference on Formal Methods and Models for Co-Design (MEMOCODE 2003), 2003

From Algorithm Graph Specification to Automatic Synthesis of FPGA Circuit: A Seamless Flow of Graphs Transformations.
Proceedings of the Field Programmable Logic and Application, 13th International Conference, 2003

A Methodology to Implement Real-Time Applications on Reconfigurable Circuits.
Proceedings of the International Conference on Engineering of Reconfigurable Systems and Algorithms, June 23, 2003

PROMPT: a mapping environment for telecom applications on "system-on-a-chip".
Proceedings of the 2000 International Conference on Compilers, 2000

Optimized rapid prototyping for real-time embedded heterogeneous multiprocessors.
Proceedings of the Seventh International Workshop on Hardware/Software Codesign, 1999