Nicolai Fiege

According to our database, Nicolai Fiege authored at least 12 papers between 2019 and 2026.

Collaborative distances:

• Dijkstra number of three.
• Erdős number of four.

2026

Discovering Optimal Constant Matrix Multiplication Circuits With Boolean Satisfiability.

Nicolai Fiege, Peter Zipf

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., May, 2026

Decompose, Optimize, and Reconstruct: Very Large Constant Multiplication at Scale.

Théo Cantaloube, Nicolai Fiege, Anastasia Volkova, Christine Solnon

CoRR, May, 2026

2025

Fantastic Circuits and Where to Find Them - A Holistic ILP Formulation for Model-Based Hardware Design.

Nicolai Fiege, Peter Zipf

ACM Trans. Reconfigurable Technol. Syst., 2025

Improving Boolean Satisfiability-Based Modulo Scheduling.

Nicolai Fiege, Peter Zipf

Proceedings of the 35th International Conference on Field-Programmable Logic and Applications, 2025

Multiplexer Optimizations for Virtex FPGAs.

Nicolai Fiege, Martin Hardieck, Peter Zipf

Proceedings of the 35th International Conference on Field-Programmable Logic and Applications, 2025

2024

Bit-Level Optimized Constant Multiplication Using Boolean Satisfiability.

Nicolai Fiege, Martin Kumm, Peter Zipf

IEEE Trans. Circuits Syst. I Regul. Pap., January, 2024

2023

BLOOP: Boolean Satisfiability-based Optimized Loop Pipelining.

Nicolai Fiege, Peter Zipf

ACM Trans. Reconfigurable Technol. Syst., September, 2023

2022

Optimal and Heuristic Approaches to Modulo Scheduling With Rational Initiation Intervals in Hardware Synthesis.

Patrick Sittel, Nicolai Fiege, John Wickerson, Peter Zipf

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022

Speeding Up Optimal Modulo Scheduling with Rational Initiation Intervals.

Nicolai Fiege, Patrick Sittel, Peter Zipf

Proceedings of the 32nd International Conference on Field-Programmable Logic and Applications, 2022

Optimal Binding and Port Assignment for Loop Pipelining in High-Level Synthesis.

Nicolai Fiege, Patrick Sittel, Peter Zipf

Proceedings of the 32nd International Conference on Field-Programmable Logic and Applications, 2022

Improving Energy Efficiency in Loop Pipelining by Rational-II Modulo Scheduling.

Nicolai Fiege, Patrick Sittel, Peter Zipf

Proceedings of the 30th IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, 2022

2019

Isomorphic Subgraph-based Problem Reduction for Resource Minimal Modulo Scheduling.

Patrick Sittel, Nicolai Fiege, Martin Kumm, Peter Zipf

Proceedings of the 2019 International Conference on ReConFigurable Computing and FPGAs, 2019