Nima Aghaee

Orcid: 0000-0002-8138-8443

According to our database1, Nima Aghaee authored at least 14 papers between 2009 and 2025.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Dataset
Other 

Links

On csauthors.net:

Bibliography

2025
Scalable Architecture for Intent-Based Optimal Control of Composite Systems.
Proceedings of the 22nd IEEE International Conference on Software Architecture, 2025

2015
Thermal Issues in Testing of Advanced Systems on Chip.
PhD thesis, 2015

Temperature-Gradient-Based Burn-In and Test Scheduling for 3-D Stacked ICs.
IEEE Trans. Very Large Scale Integr. Syst., 2015

A Test-Ordering Based Temperature-Cycling Acceleration Technique for 3D Stacked ICs.
J. Electron. Test., 2015

Efficient Test Application for Rapid Multi-Temperature Testing.
Proceedings of the 25th edition on Great Lakes Symposium on VLSI, GLVLSI 2015, Pittsburgh, PA, USA, May 20, 2015

An integrated temperature-cycling acceleration and test technique for 3D stacked ICs.
Proceedings of the 20th Asia and South Pacific Design Automation Conference, 2015

2014
Process-Variation Aware Multi-temperature Test Scheduling.
Proceedings of the 2014 27th International Conference on VLSI Design, 2014

An efficient temperature-gradient based burn-in technique for 3D stacked ICs.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2014

2013
Process-Variation and Temperature Aware SoC Test Scheduling Technique.
J. Electron. Test., 2013

Temperature-gradient based test scheduling for 3D stacked ICs.
Proceedings of the 20th IEEE International Conference on Electronics, 2013

2011
Process-variation and temperature aware soc test scheduling using particle swarm optimization.
Proceedings of the 6th IEEE International Design and Test Workshop, 2011

Adaptive Temperature-Aware SoC Test Scheduling Considering Process Variation.
Proceedings of the 14th Euromicro Conference on Digital System Design, 2011

2010
Temperature-Aware SoC Test Scheduling Considering Inter-Chip Process Variation.
Proceedings of the 19th IEEE Asian Test Symposium, 2010

2009
Design of a pipelined R4SDF processor.
Proceedings of the 17th European Signal Processing Conference, 2009


  Loading...