Mohammad Eshghi

According to our database1, Mohammad Eshghi authored at least 42 papers between 1995 and 2020.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.



In proceedings 
PhD thesis 


Online presence:



Secure decentralized peer-to-peer training of deep neural networks based on distributed ledger technology.
J. Supercomput., 2020

General Method to Design Reversible Universal n-Bit Up/Down Counters.
J. Circuits Syst. Comput., 2020

Detection of premature ventricular contraction (PVC) using linear and nonlinear techniques: an experimental study.
Clust. Comput., 2020

Low-cost and compact design method for reversible sequential circuits.
J. Supercomput., 2019

Lifetime-aware scheduling in high level synthesis.
Microelectron. Reliab., 2018

Cost and power efficient FPGA based stereo vision system using directional graph transform.
J. Vis. Commun. Image Represent., 2018

An approach for safer navigation under severe hurricane damage.
J. Reliab. Intell. Environ., 2018

FPGA based real-time on-road stereo vision system.
J. Syst. Archit., 2017

Comparison of the deep-learning-based automated segmentation methods for the head sectioned images of the virtual Korean human project.
Proceedings of the Fifteenth IAPR International Conference on Machine Vision Applications, 2017

Automatic segmentation of head anatomical structures from sparsely-annotated images.
Proceedings of the IEEE International Conference on Cyborg and Bionic Systems, 2017

Noise and Process Variation Tolerant, Low-Power, High-Speed, and Low-Energy Full Adders in CNFET Technology.
IEEE Trans. Very Large Scale Integr. Syst., 2016

An Ultra-Low-Power 9T SRAM Cell Based on Threshold Voltage Techniques.
Circuits Syst. Signal Process., 2016

A fast placement algorithm for embedded just-in-time reconfigurable extensible processing platform.
J. Supercomput., 2015

A Low-Power Multiplier Using an Efficient Single-Supply Voltage Level Converter.
J. Circuits Syst. Comput., 2015

High-Speed, High-Frequency and Low-PDP, CNFET Full Adder Cells.
J. Circuits Syst. Comput., 2015

A novel low-energy CNFET-based full adder cell using pass-transistor logic.
Int. J. High Perform. Syst. Archit., 2015

Erratum to: A Symmetric, Multi-Threshold, High-Speed and Efficient-Energy 1-Bit Full Adder Cell Design Using CNFET Technology.
Circuits Syst. Signal Process., 2015

A Symmetric, Multi-Threshold, High-Speed and Efficient-Energy 1-Bit Full Adder Cell Design Using CNFET Technology.
Circuits Syst. Signal Process., 2015

Active noise control using an adaptive bacterial foraging optimization algorithm.
Signal Image Video Process., 2014

An optimized design of optical networks using evolutionary algorithms.
J. High Speed Networks, 2014

Chaotic image encryption system using phase-magnitude transformation and pixel substitution.
Telecommun. Syst., 2013

Image encryption based on chaotic tent map in time and frequency domains.
ISC Int. J. Inf. Secur., 2013

Design and Optimization of Single and Multiple-Loop Reversible and Quantum Feedback Circuits.
J. Circuits Syst. Comput., 2012

Mehrab Maps: One-Dimensional Piecewise nonlinear Chaotic Maps.
Int. J. Bifurc. Chaos, 2012

Non-linear active noise cancellation using a bacterial foraging optimisation algorithm.
IET Signal Process., 2012

Design and implementation of a real time and train less eye state recognition system.
EURASIP J. Adv. Signal Process., 2012

Clustered NOC, a suitable design for group communications in Network on Chip.
Comput. Electr. Eng., 2012

Controlled gates for multi-level quantum computation.
Quantum Inf. Process., 2011

Design of 3-Input Reversible Programmable Logic Array.
J. Circuits Syst. Comput., 2011

Design of an ASIP IDEA crypto processor.
Proceedings of the 2nd IEEE International Conference on Networked Embedded Systems for Enterprise Applications, 2011

PWL approximation of hyperbolic tangent and the first derivative for VLSI implementation.
Proceedings of the 23rd Canadian Conference on Electrical and Computer Engineering, 2010

An approach to recognize and pronounce words with alternative pronunciations in Farsi.
Proceedings of the 23rd Canadian Conference on Electrical and Computer Engineering, 2010

On figures of merit in reversible and quantum logic designs.
Quantum Inf. Process., 2009

Optimized Reversible Multiplier Circuit.
J. Circuits Syst. Comput., 2009

Efficient MRC-Based Residue to Binary Converters for the New Moduli Sets {2<sup>2<i>n</i></sup>, 2<sup><i>n</i></sup> -1, 2<sup><i>n</i>+1</sup> -1} and {2<sup>2<i>n</i></sup>, 2<sup><i>n</i></sup> -1, 2<sup><i>n</i>-1</sup> -1}.
IEICE Trans. Inf. Syst., 2009

Half-Zone Quantization Based Algorithm for Information Hiding.
Proceedings of the Fifth International Conference on Intelligent Information Hiding and Multimedia Signal Processing (IIH-MSP 2009), 2009

Design of a pipelined R4SDF processor.
Proceedings of the 17th European Signal Processing Conference, 2009

Heuristic methods to use <i>don't cares</i> in automated design of reversible and quantum logic circuits.
Quantum Inf. Process., 2008

An efficient hybrid solution for pronouncing Farsi text.
Int. J. Speech Technol., 2007

The Computer-Brain Interface.
Proceedings of the 22nd International Conference on Computers and Their Applications, 2007

Design and implementation of a new Persian digits OCR algorithm on FPGA chips.
Proceedings of the 13th European Signal Processing Conference, 2005

A parallel binary structured LMS algorithm for transversal adaptive filters.
J. VLSI Signal Process., 1995