Petru Eles

According to our database1, Petru Eles authored at least 225 papers between 1992 and 2019.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

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Other 

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Bibliography

2019
Scheduling optimization with partitioning for mixed-criticality systems.
Journal of Systems Architecture - Embedded Systems Design, 2019

2018 Embedded Systems Week (ESWEEK) in Torino.
IEEE Design & Test, 2019

On Reachability in Parameterized Phaser Programs.
Proceedings of the Tools and Algorithms for the Construction and Analysis of Systems, 2019

Cache-Aware Kernel Tiling: An Approach for System-Level Performance Optimization of GPU-Based Applications.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2019

Runtime Resource Management with Workload Prediction.
Proceedings of the 56th Annual Design Automation Conference 2019, 2019

Partitioned and overhead-aware scheduling of mixed-criticality real-time systems.
Proceedings of the 24th Asia and South Pacific Design Automation Conference, 2019

2018
Guest Editorial for the Special Issue of ESWEEK 2016.
ACM Trans. Embedded Comput. Syst., 2018

Editorial.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2018

Optimization of Message Encryption for Real-Time Applications in Embedded Systems.
IEEE Trans. Computers, 2018

Roundtable: Machine Learning for Embedded Systems: Hype or Lasting Impact?
IEEE Design & Test, 2018

Control-Quality-Driven Design of Embedded Control Systems with Stability Guarantees.
IEEE Design & Test, 2018

Measurement Based Execution Time Analysis of GPGPU Programs via SE+GA.
Proceedings of the 21st Euromicro Conference on Digital System Design, 2018

Stability-aware integrated routing and scheduling for control applications in Ethernet networks.
Proceedings of the 2018 Design, Automation & Test in Europe Conference & Exhibition, 2018

2017
Networked Real-Time Embedded Systems.
Proceedings of the Handbook of Hardware/Software Codesign., 2017

Introduction to Hardware/Software Codesign.
Proceedings of the Handbook of Hardware/Software Codesign., 2017

Probabilistic Analysis of Electronic Systems via Adaptive Hierarchical Interpolation.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2017

Workload prediction for runtime resource management.
Proceedings of the IEEE Nordic Circuits and Systems Conference, 2017

Safety verification of phaser programs.
Proceedings of the 2017 Formal Methods in Computer Aided Design, 2017

Two-Phase Interarrival Time Prediction for Runtime Resource Management.
Proceedings of the Euromicro Conference on Digital System Design, 2017

Latency-Aware Packet Processing on CPU-GPU Heterogeneous Systems.
Proceedings of the 54th Annual Design Automation Conference, 2017

2016
Correlation-Aware Probabilistic Timing Analysis for the Dynamic Segment of FlexRay.
ACM Trans. Embedded Comput. Syst., 2016

Power-Aware Design Techniques of Secure Multimode Embedded Systems.
ACM Trans. Embedded Comput. Syst., 2016

Guest Editorial for Special Issue of ESWEEK 2015.
ACM Trans. Embedded Comput. Syst., 2016

A Reconfigurable Framework for Performance Enhancement With Dynamic FPGA Configuration Prefetching.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2016

Analysis and Design of Real-Time Servers for Control Applications.
IEEE Trans. Computers, 2016

Counting dynamically synchronizing processes.
STTT, 2016

Systematic detection of memory related performance bottlenecks in GPGPU programs.
Journal of Systems Architecture - Embedded Systems Design, 2016

Lazy Constrained Monotonic Abstraction.
Proceedings of the Verification, Model Checking, and Abstract Interpretation, 2016

Intrusion-Damage Assessment and Mitigation in Cyber-Physical Systems for Control Applications.
Proceedings of the 24th International Conference on Real-Time Networks and Systems, 2016

Self-triggered controllers and hard real-time guarantees.
Proceedings of the 2016 Design, Automation & Test in Europe Conference & Exhibition, 2016

SPARTA: A scheduling policy for thwarting differential power analysis attacks.
Proceedings of the 21st Asia and South Pacific Design Automation Conference, 2016

2015
Temperature-Centric Reliability Analysis and Optimization of Electronic Systems Under Process Variation.
IEEE Trans. VLSI Syst., 2015

Temperature-Gradient-Based Burn-In and Test Scheduling for 3-D Stacked ICs.
IEEE Trans. VLSI Syst., 2015

Stability of Online Resource Managers for Distributed Systems under Execution Time Variations.
ACM Trans. Embedded Comput. Syst., 2015

A Test-Ordering Based Temperature-Cycling Acceleration Technique for 3D Stacked ICs.
J. Electronic Testing, 2015

Abstracting and Counting Synchronizing Processes.
Proceedings of the Verification, Model Checking, and Abstract Interpretation, 2015

Jfair: a scheduling algorithm to stabilize control applications.
Proceedings of the 21st IEEE Real-Time and Embedded Technology and Applications Symposium, 2015

Perception-Aware Power Management for Mobile Games via Dynamic Resolution Scaling.
Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, 2015

Efficient Test Application for Rapid Multi-Temperature Testing.
Proceedings of the 25th edition on Great Lakes Symposium on VLSI, GLVLSI 2015, Pittsburgh, PA, USA, May 20, 2015

On-the-fly energy minimization for multi-mode real-time systems on heterogeneous platforms.
Proceedings of the 13th IEEE Symposium on Embedded Systems For Real-time Multimedia, 2015

Probabilistic Response Time and Joint Analysis of Periodic Tasks.
Proceedings of the 27th Euromicro Conference on Real-Time Systems, 2015

An integrated temperature-cycling acceleration and test technique for 3D stacked ICs.
Proceedings of the 20th Asia and South Pacific Design Automation Conference, 2015

2014
Quantifying Notions of Extensibility in FlexRay Schedule Synthesis.
ACM Trans. Design Autom. Electr. Syst., 2014

Probabilistic Analysis of Power and Temperature Under Process Variation for Electronic System Design.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2014

Time-Predictable Embedded Software on Multi-Core Platforms: Analysis and Optimization.
Foundations and Trends in Electronic Design Automation, 2014

Process-Variation Aware Multi-temperature Test Scheduling.
Proceedings of the 2014 27th International Conference on VLSI Design and 2014 13th International Conference on Embedded Systems, 2014

Schedulability analysis of Ethernet AVB switches.
Proceedings of the 2014 IEEE 20th International Conference on Embedded and Real-Time Computing Systems and Applications, 2014

Robustness Analysis of Real-Time Scheduling Against Differential Power Analysis Attacks.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2014

Automated software testing of memory performance in embedded GPUs.
Proceedings of the 2014 International Conference on Embedded Software, 2014

Bandwidth-efficient controller-server co-design with stability guarantees.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2014

An efficient temperature-gradient based burn-in technique for 3D stacked ICs.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2014

Saving energy without defying deadlines on mobile GPU-based heterogeneous systems.
Proceedings of the 2014 International Conference on Hardware/Software Codesign and System Synthesis, 2014

Statistical analysis of process variation based on indirect measurements for electronic system design.
Proceedings of the 19th Asia and South Pacific Design Automation Conference, 2014

2013
Stability of adaptive feedback-based resource managers for systems with execution time variations.
Real-Time Systems, 2013

Process-Variation and Temperature Aware SoC Test Scheduling Technique.
J. Electronic Testing, 2013

General purpose computing on low-power embedded GPUs: Has it come of age?
Proceedings of the 2013 International Conference on Embedded Computer Systems: Architectures, 2013

Designing Bandwidth-Efficient Stabilizing Control Servers.
Proceedings of the IEEE 34th Real-Time Systems Symposium, 2013

Energy-aware design of secure multi-mode real-time embedded systems with FPGA co-processors.
Proceedings of the 21st International Conference on Real-Time Networks and Systems, 2013

Temperature-gradient based test scheduling for 3D stacked ICs.
Proceedings of the 20th IEEE International Conference on Electronics, 2013

Stability-aware analysis and design of embedded control systems.
Proceedings of the International Conference on Embedded Software, 2013

Probabilistic Timing Analysis for the Dynamic Segment of FlexRay.
Proceedings of the 25th Euromicro Conference on Real-Time Systems, 2013

Dynamic configuration prefetching based on piecewise linear prediction.
Proceedings of the Design, Automation and Test in Europe, 2013

Optimization of secure embedded systems with dynamic task sets.
Proceedings of the Design, Automation and Test in Europe, 2013

Control-quality driven design of cyber-physical systems with robustness guarantees.
Proceedings of the Design, Automation and Test in Europe, 2013

2012
Temperature-Aware Idle Time Distribution for Leakage Energy Optimization.
IEEE Trans. VLSI Syst., 2012

Scheduling and Optimization of Fault-Tolerant Embedded Systems with Transparency/Performance Trade-Offs.
ACM Trans. Embedded Comput. Syst., 2012

Introduction to the Special Section on ESTIMedia'08.
ACM Trans. Embedded Comput. Syst., 2012

Low-Energy Standby-Sparing for Hard Real-Time Systems.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2012

Customizing Instruction Set Extensible Reconfigurable Processors Using GPUs.
Proceedings of the 25th International Conference on VLSI Design, 2012

On the timing analysis of the dynamic segment of FlexRay.
Proceedings of the 7th IEEE International Symposium on Industrial Embedded Systems, 2012

Designing High-Quality Embedded Control Systems with Guaranteed Stability.
Proceedings of the 33rd IEEE Real-Time Systems Symposium, 2012

Context-Aware Speculative Prefetch for Soft Real-Time Applications.
Proceedings of the 2012 IEEE International Conference on Embedded and Real-Time Computing Systems and Applications, 2012

Reliability-Aware Instruction Set Customization for ASIPs with Hardened Logic.
Proceedings of the 2012 IEEE International Conference on Embedded and Real-Time Computing Systems and Applications, 2012

Schedulability Analysis for the Dynamic Segment of FlexRay: A Generalization to Slot Multiplexing.
Proceedings of the 2012 IEEE 18th Real Time and Embedded Technology and Applications Symposium, 2012

Minimization of average execution time based on speculative FPGA configuration prefetch.
Proceedings of the 2012 International Conference on Reconfigurable Computing and FPGAs, 2012

Control-Quality Optimization for Distributed Embedded Systems with Adaptive Fault Tolerance.
Proceedings of the 24th Euromicro Conference on Real-Time Systems, 2012

A scalable GPU-based approach to accelerate the multiple-choice knapsack problem.
Proceedings of the 2012 Design, Automation & Test in Europe Conference & Exhibition, 2012

Co-design techniques for distributed real-time embedded systems with communication security constraints.
Proceedings of the 2012 Design, Automation & Test in Europe Conference & Exhibition, 2012

Steady-state dynamic temperature analysis and reliability optimization for embedded multiprocessor systems.
Proceedings of the 49th Annual Design Automation Conference 2012, 2012

Automatic Test Program Generation for Out-of-Order Superscalar Processors.
Proceedings of the 21st IEEE Asian Test Symposium, 2012

2011
Quasi-Static Voltage Scaling for Energy Minimization With Time Constraints.
IEEE Trans. VLSI Syst., 2011

Control-Quality Driven Task Mapping for Distributed Embedded Control Systems.
Proceedings of the 17th IEEE International Conference on Embedded and Real-Time Computing Systems and Applications, 2011

Bus Access Design for Combined Worst and Average Case Execution Time Optimization of Predictable Real-Time Applications on Multiprocessor Systems-on-Chip.
Proceedings of the 17th IEEE Real-Time and Embedded Technology and Applications Symposium, 2011

Process-variation and temperature aware soc test scheduling using particle swarm optimization.
Proceedings of the 6th IEEE International Design and Test Workshop, 2011

Reliability-aware frame packing for the static segment of flexray.
Proceedings of the 11th International Conference on Embedded Software, 2011

Stability Conditions of On-line Resource Managers for Systems with Execution Time Variations.
Proceedings of the 23rd Euromicro Conference on Real-Time Systems, 2011

Adaptive Temperature-Aware SoC Test Scheduling Considering Process Variation.
Proceedings of the 14th Euromicro Conference on Digital System Design, 2011

Design Optimization and Synthesis of FlexRay Parameters for Embedded Control Applications.
Proceedings of the Sixth IEEE International Symposium on Electronic Design, 2011

Predictable Worst-Case Execution Time Analysis for Multiprocessor Systems-on-Chip.
Proceedings of the Sixth IEEE International Symposium on Electronic Design, 2011

On-line Temperature-Aware Idle Time Distribution for Leakage Energy Optimization.
Proceedings of the Sixth IEEE International Symposium on Electronic Design, 2011

Optimization of message encryption for distributed embedded systems with real-time constraints.
Proceedings of the 14th IEEE International Symposium on Design and Diagnostics of Electronic Circuits & Systems, 2011

On the quantification of sustainability and extensibility of FlexRay schedules.
Proceedings of the 48th Design Automation Conference, 2011

Performance optimization of error detection based on speculative reconfiguration.
Proceedings of the 48th Design Automation Conference, 2011

2010
Scheduling for Fault-Tolerant Communication on the Static Segment of FlexRay.
Proceedings of the 31st IEEE Real-Time Systems Symposium, 2010

Dynamic Scheduling and Control-Quality Optimization of Self-Triggered Control Applications.
Proceedings of the 31st IEEE Real-Time Systems Symposium, 2010

Low Overhead Dynamic QoS Optimization under Variable Task Execution Times.
Proceedings of the 16th IEEE International Conference on Embedded and Real-Time Computing Systems and Applications, 2010

Value-based scheduling of distributed fault-tolerant real-time systems with soft and hard timing constraints.
Proceedings of the 8th IEEE Workshop on Embedded Systems for Real-Time Multimedia, 2010

Message from the chairs.
Proceedings of the 8th IEEE Workshop on Embedded Systems for Real-Time Multimedia, 2010

Multi-temperature testing for core-based system-on-chip.
Proceedings of the Design, Automation and Test in Europe, 2010

Temperature-aware idle time distribution for energy optimization with dynamic voltage scaling.
Proceedings of the Design, Automation and Test in Europe, 2010

Hardware/software optimization of error detection implementation for real-time embedded systems.
Proceedings of the 8th International Conference on Hardware/Software Codesign and System Synthesis, 2010

Temperature-Aware SoC Test Scheduling Considering Inter-Chip Process Variation.
Proceedings of the 19th IEEE Asian Test Symposium, 2010

2009
Design Optimization of Time- and Cost-Constrained Fault-Tolerant Embedded Systems With Checkpointing and Replication.
IEEE Trans. VLSI Syst., 2009

Predictable Implementation of Real-Time Applications on Multiprocessor Systems on Chip.
Proceedings of the 9th Intl. Workshop on Worst-Case Execution Time Analysis, 2009

Immune Genetic Algorithms for Optimization of Task Priorities and FlexRay Frame Identifiers.
Proceedings of the 15th IEEE International Conference on Embedded and Real-Time Computing Systems and Applications, 2009

2009 IEEE/ACM/IFIP 7th workshop on embedded systems for Real-Time multimedia (ESTIMedia 2009).
Proceedings of the 7th IEEE/ACM/IFIP Workshop on Embedded Systems for Real-Time Multimedia, 2009

Thermal-Aware Test Scheduling for Core-Based SoC in an Abort-on-First-Fail Test Environment.
Proceedings of the 12th Euromicro Conference on Digital System Design, 2009

Integrated scheduling and synthesis of control applications on distributed embedded systems.
Proceedings of the Design, Automation and Test in Europe, 2009

Analysis and optimization of fault-tolerant embedded systems with hardened processors.
Proceedings of the Design, Automation and Test in Europe, 2009

Quality-driven synthesis of embedded multi-mode control systems.
Proceedings of the 46th Design Automation Conference, 2009

On-line thermal aware dynamic voltage scaling for energy optimization with frequency/temperature dependency consideration.
Proceedings of the 46th Design Automation Conference, 2009

A standby-sparing technique with low energy-overhead for fault-tolerant hard real-time systems.
Proceedings of the 7th International Conference on Hardware/Software Codesign and System Synthesis, 2009

2008
Task mapping and priority assignment for soft real-time applications under deadline miss ratio constraints.
ACM Trans. Embedded Comput. Syst., 2008

Timing analysis of the FlexRay communication protocol.
Real-Time Systems, 2008

Analysis and Optimisation of Hierarchically Scheduled Multiprocessor Embedded Systems.
International Journal of Parallel Programming, 2008

Model validation for embedded systems using formal method-aided simulation.
IET Computers & Digital Techniques, 2008

Thermal-Aware SoC Test Scheduling with Test Set Partitioning and Interleaving.
J. Electronic Testing, 2008

Predictable Implementation of Real-Time Applications on Multiprocessor Systems-on-Chip.
Proceedings of the 21st International Conference on VLSI Design (VLSI Design 2008), 2008

Synthesis of Flexible Fault-Tolerant Schedules with Preemption for Mixed Soft and Hard Real-Time Systems.
Proceedings of the 11th Euromicro Conference on Digital System Design: Architectures, 2008

Temperature-Aware Task Mapping for Energy Optimization with Dynamic Voltage Scaling.
Proceedings of the 11th IEEE Workshop on Design & Diagnostics of Electronic Circuits & Systems (DDECS 2008), 2008

A Simulation Methodology for Worst-Case Response Time Estimation of Distributed Real-Time Systems.
Proceedings of the Design, Automation and Test in Europe, 2008

Test-Architecture Optimization and Test Scheduling for SOCs with Core-Level Expansion of Compressed Test Patterns.
Proceedings of the Design, Automation and Test in Europe, 2008

Scheduling of Fault-Tolerant Embedded Systems with Soft and Hard Timing Constraints.
Proceedings of the Design, Automation and Test in Europe, 2008

Synthesis of Fault-Tolerant Embedded Systems.
Proceedings of the Design, Automation and Test in Europe, 2008

Temperature-Aware Voltage Selection for Energy Optimization.
Proceedings of the Design, Automation and Test in Europe, 2008

Simulation-Driven Thermal-Safe Test Time Minimization for System-on-Chip.
Proceedings of the 17th IEEE Asian Test Symposium, 2008

2007
Energy Optimization of Multiprocessor Systems on Chip by Voltage Selection.
IEEE Trans. VLSI Syst., 2007

Fault-aware Communication Mapping for NoCs with Guaranteed Latency.
International Journal of Parallel Programming, 2007

Formal verification of component-based designs.
Design Autom. for Emb. Sys., 2007

Bus Access Optimization for Predictable Implementation of Real-Time Applications on Multiprocessor Systems-on-Chip.
Proceedings of the 28th IEEE Real-Time Systems Symposium (RTSS 2007), 2007

What impacts course evaluation?
Proceedings of the 12th Annual SIGCSE Conference on Innovation and Technology in Computer Science Education, 2007

A heuristic for thermal-safe SoC test scheduling.
Proceedings of the 2007 IEEE International Test Conference, 2007

Transactor-based Formal Verification of Real-time Embedded Systems.
Proceedings of the Forum on specification and Design Languages, 2007

A Heuristic for Concurrent SOC Test Scheduling with Compression and Sharing.
Proceedings of the 10th IEEE Workshop on Design & Diagnostics of Electronic Circuits & Systems (DDECS 2007), 2007

Bus access optimisation for FlexRay-based distributed embedded systems.
Proceedings of the 2007 Design, Automation and Test in Europe Conference and Exposition, 2007

Optimized integration of test compression and sharing for SOC testing.
Proceedings of the 2007 Design, Automation and Test in Europe Conference and Exposition, 2007

Scheduling and voltage scaling for energy/reliability trade-offs in fault-tolerant time-triggered embedded systems.
Proceedings of the 5th International Conference on Hardware/Software Codesign and System Synthesis, 2007

Real-time applications with stochastic task execution times - analysis and optimisation.
Springer, ISBN: 978-1-4020-5505-8, 2007

2006
Quasi-Static Assignment of Voltages and Optional Cycles in Imprecise-Computation Systems With Energy Considerations.
IEEE Trans. VLSI Syst., 2006

Analysis and optimization of distributed real-time embedded systems.
ACM Trans. Design Autom. Electr. Syst., 2006

Dual Flow Nets: Modeling the control/data-flow relation in embedded systems.
ACM Trans. Embedded Comput. Syst., 2006

Test Time Minimization for Hybrid BIST of Core-Based Systems.
J. Comput. Sci. Technol., 2006

A Quasi-Static Approach to Minimizing Energy Consumption in Real-Time Systems under Reward Constraints.
Proceedings of the 12th IEEE Conference on Embedded and Real-Time Computing Systems and Applications (RTCSA 2006), 2006

Mapping of Fault-Tolerant Applications with Transparency on Distributed Embedded Systems*.
Proceedings of the Ninth Euromicro Conference on Digital System Design: Architectures, Methods and Tools (DSD 2006), 30 August, 2006

Synthesis of Fault-Tolerant Embedded Systems with Checkpointing and Replication.
Proceedings of the Third IEEE International Workshop on Electronic Design, 2006

Buffer space optimisation with communication synthesis and traffic shaping for NoCs.
Proceedings of the Conference on Design, Automation and Test in Europe, 2006

Formal verification of systemc designs using a petri-net based representation.
Proceedings of the Conference on Design, Automation and Test in Europe, 2006

Synthesis of fault-tolerant schedules with transparency/performance trade-offs for distributed embedded systems.
Proceedings of the Conference on Design, Automation and Test in Europe, 2006

Power constrained and defect-probability driven SoC test scheduling with test set partitioning.
Proceedings of the Conference on Design, Automation and Test in Europe, 2006

2005
Schedulability-driven frame packing for multicluster distributed embedded systems.
ACM Trans. Embedded Comput. Syst., 2005

Cosynthesis of energy-efficient multimode embedded systems with consideration of mode-execution probabilities.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2005

A Wiring-Aware Approach to Minimizing Built-In Self-Test Overhead.
J. Comput. Sci. Technol., 2005

Optimization of Hierarchically Scheduled Heterogeneous Embedded Systems.
Proceedings of the 11th IEEE International Conference on Embedded and Real-Time Computing Systems and Applications (RTCSA 2005), 2005

Quasi-Static Scheduling for Multiprocessor Real-Time Systems with Hard and Soft Tasks.
Proceedings of the 11th IEEE International Conference on Embedded and Real-Time Computing Systems and Applications (RTCSA 2005), 2005

Power-Composition Profile Driven Co-Synthesis with Power Management Selection for Dynamic and Leakage Energy Reduction.
Proceedings of the Eighth Euromicro Symposium on Digital Systems Design (DSD 2005), 30 August, 2005

Optimization of a Bus-based Test Data Transportation Mechanism in System-on-Chip.
Proceedings of the Eighth Euromicro Symposium on Digital Systems Design (DSD 2005), 30 August, 2005

Validation of Embedded Systems Using Formal Method Aided Simulation.
Proceedings of the Eighth Euromicro Symposium on Digital Systems Design (DSD 2005), 30 August, 2005

Power-Constrained Hybrid BIST Test Scheduling in an Abort-on-First-Fail Test Environment.
Proceedings of the Eighth Euromicro Symposium on Digital Systems Design (DSD 2005), 30 August, 2005

Design Optimization of Time-and Cost-Constrained Fault-Tolerant Distributed Embedded Systems.
Proceedings of the 2005 Design, 2005

Quasi-Static Voltage Scaling for Energy Minimization with Time Constraints.
Proceedings of the 2005 Design, 2005

Fault and energy-aware communication mapping with guaranteed latency for applications implemented on NoC.
Proceedings of the 42nd Design Automation Conference, 2005

Quasi-static assignment of voltages and optional cycles for maximizing rewards in real-time systems with energy c-onstraints.
Proceedings of the 42nd Design Automation Conference, 2005

SOC Test Scheduling with Test Set Sharing and Broadcasting.
Proceedings of the 14th Asian Test Symposium (ATS 2005), 2005

2004
Scheduling and mapping in an incremental design methodology for distributed real-time embedded systems.
IEEE Trans. VLSI Syst., 2004

Iterative schedule optimization for voltage scalable distributed embedded systems.
ACM Trans. Embedded Comput. Syst., 2004

Schedulability analysis of applications with stochastic task execution times.
ACM Trans. Embedded Comput. Syst., 2004

Schedulability-Driven Communication Synthesis for Time Triggered Embedded Systems.
Real-Time Systems, 2004

Guest Editors' Introduction: Designing Real-Time Embedded Multimedia Systems.
IEEE Design & Test of Computers, 2004

Optimization of Soft Real-Time Systems with Deadline Miss Ratio Constraints.
Proceedings of the 10th IEEE Real-Time and Embedded Technology and Applications Symposium (RTAS 2004), 2004

Simultaneous communication and processor voltage scaling for dynamic and leakage energy reduction in time-constrained systems.
Proceedings of the 2004 International Conference on Computer-Aided Design, 2004

A Formal Verification Approach for IP-based Designs.
Proceedings of the Forum on specification and Design Languages, 2004

Schedulability-Driven Partitioning and Mapping for Multi-Cluster Real-Time Systems.
Proceedings of the 16th Euromicro Conference on Real-Time Systems (ECRTS 2004), 30 June, 2004

A Heuristic for Wiring-Aware Built-In Self-Test Synthesis.
Proceedings of the 2004 Euromicro Symposium on Digital Systems Design (DSD 2004), Architectures, Methods and Tools, 31 August, 2004

A Formal Verification Methodology for IP-based Designs.
Proceedings of the 2004 Euromicro Symposium on Digital Systems Design (DSD 2004), Architectures, Methods and Tools, 31 August, 2004

Static Scheduling of Monoprocessor Real-Time Systems composed of Hard and Soft Tasks.
Proceedings of the 2nd IEEE International Workshop on Electronic Design, 2004

Design Optimization of Multi-Cluster Embedded Systems for Real-Time Application.
Proceedings of the 2004 Design, 2004

Quasi-Static Scheduling for Real-Time Systems with Hard and Soft Tasks.
Proceedings of the 2004 Design, 2004

Overhead-Conscious Voltage Selection for Dynamic and Leakage Energy Reduction of Time-Constrained Systems.
Proceedings of the 2004 Design, 2004

Hybrid BIST Test Scheduling Based on Defect Probabilities.
Proceedings of the 13th Asian Test Symposium (ATS 2004), 2004

Analysis and synthesis of distributed real-time embedded systems.
Springer, ISBN: 978-1-4020-2872-4, 2004

System-level design techniques for energy-efficient embedded systems.
Springer, ISBN: 978-1-4020-7750-0, 2004

2003
Modeling and formal verification of embedded systems based on a Petri net representation.
Journal of Systems Architecture, 2003

Schedulability-driven frame packing for multi-cluster distributed embedded systems.
Proceedings of the 2003 Conference on Languages, 2003

Schedulability Analysis for Distributed Heterogeneous Time/Event Triggered Real-Time Systems.
Proceedings of the 15th Euromicro Conference on Real-Time Systems (ECRTS 2003), 2003

Buffer and Controller Minimisation for Time-Constrained Testing of System-On-Chip.
Proceedings of the 18th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2003), 2003

Hybrid BIST Time Minimization for Core-Based Systems with STUMPS Architecture.
Proceedings of the 18th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2003), 2003

Scheduling and Mapping of Conditional Task Graphs for the Synthesis of Low Power Embedded Systems.
Proceedings of the 2003 Design, 2003

A Co-Design Methodology for Energy-Efficient Multi-Mode Embedded Systems with Consideration of Mode Execution Probabilities.
Proceedings of the 2003 Design, 2003

Schedulability Analysis and Optimization for the Synthesis of Multi-Cluster Distributed Embedded Systems.
Proceedings of the 2003 Design, 2003

Design optimization of mixed time/event-triggered distributed embedded systems.
Proceedings of the 1st IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis, 2003

2002
Synthesizing Energy-Efficient Embedded Systems with LOPOCOS.
Design Autom. for Emb. Sys., 2002

Editorial.
Design Autom. for Emb. Sys., 2002

Formal Verification in a Component-Based Reuse Methodology.
Proceedings of the 15th International Symposium on System Synthesis (ISSS 2002), 2002

Schedulability analysis of multiprocessor real-time applications with stochastic task execution times.
Proceedings of the 2002 IEEE/ACM International Conference on Computer-aided Design, 2002

Energy-Efficient Mapping and Scheduling for DVS Enabled Distributed Embedded Systems.
Proceedings of the 2002 Design, 2002

Symbolic model checking of Dual Transition Petri Nets.
Proceedings of the Tenth International Symposium on Hardware/Software Codesign, 2002

Holistic scheduling and analysis of mixed time/event-triggered distributed embedded systems.
Proceedings of the Tenth International Symposium on Hardware/Software Codesign, 2002

2001
SOCWARE: A New Swedish Design Cluster for System-on-Chip.
Proceedings of the 2001 International Conference on Microelectronics Systems Education, 2001

Memory and Time-Efficient Schedulability Analysis of Task Sets with Stochastic Execution Time.
Proceedings of the 13th Euromicro Conference on Real-Time Systems (ECRTS 2001), 2001

Hierarchical Modeling and Verification of Embedded Systems.
Proceedings of the Euromicro Symposium on Digital Systems Design 2001 (Euro-DSD 2001), 2001

An Approach to Incremental Design of Distributed Embedded Systems.
Proceedings of the 38th Design Automation Conference, 2001

Minimizing system modification in an incremental design approach.
Proceedings of the Ninth International Symposium on Hardware/Software Codesign, 2001

2000
Scheduling with bus access optimization for distributed embedded systems.
IEEE Trans. VLSI Syst., 2000

Verification of Embedded Systems using a Petri Net based Representation.
Proceedings of the 13th International Symposium on System Synthesis, 2000

Modeling of Real-Time Embedded Systems in an Object-Oriented Design Environment with UML.
Proceedings of the 3rd International Symposium on Object-Oriented Real-Time Distributed Computing (ISORC 2000), 2000

Definitions of Equivalence for Transformational Synthesis of Embedded Systems.
Proceedings of the 6th International Conference on Engineering of Complex Computer Systems (ICECCS 2000), 2000

Formal Coverification of Embedded Systems Using Model Checking.
Proceedings of the 26th EUROMICRO 2000 Conference, 2000

Schedulability analysis for systems with data and control dependencies.
Proceedings of the 12th Euromicro Conference on Real-Time Systems (ECRTS 2000), 2000

Bus Access Optimization for Distributed Embedded Systems Based on Schedulability Analysis.
Proceedings of the 2000 Design, 2000

Performance estimation for embedded systems with data and control dependencies.
Proceedings of the Eighth International Workshop on Hardware/Software Codesign, 2000

1999
An Improved Scheduling Technique for Time-Triggered Embedded Systems.
Proceedings of the 25th EUROMICRO '99 Conference, 1999

Scheduling with optimized communication for time-triggered embedded systems.
Proceedings of the Seventh International Workshop on Hardware/Software Codesign, 1999

1998
Scheduling under data and control dependencies for heterogeneous architectures.
Proceedings of the International Conference on Computer Design: VLSI in Computers and Processors, 1998

Process Scheduling for Performance Estimation and Synthesis of Hardware/Software Systems.
Proceedings of the 24th EUROMICRO '98 Conference, 1998

Scheduling of Conditional Process Graphs for the Synthesis of Embedded Systems.
Proceedings of the 1998 Design, 1998

1997
Post-synthesis back-annotation of timing information in behavioral VHDL.
Journal of Systems Architecture, 1997

System Level Hardware/Software Partitioning Based on Simulated Annealing and Tabu Search.
Design Autom. for Emb. Sys., 1997

1996
Synthesis of systems specified as interacting VHDL processes.
Integration, 1996

Hardware/Software Partitioning with Iterative Improvement Heuristics.
Proceedings of the 9th International Symposium on System Synthesis, 1996

Automatic Parallelization of a Petri Net-Based Design Representation for High-Level Synthesis.
Proceedings of the 22rd EUROMICRO Conference '96, 1996

Hardware/software partitioning of VHDL system specifications.
Proceedings of the conference on European design automation, 1996

1995
Timing constraint specification and synthesis in behavioral VHDL.
Proceedings of the Proceedings EURO-DAC'95, 1995

1994
Synthesis of VHDL concurrent processes.
Proceedings of the Proceedings EURO-DAC'94, 1994

VHDL system-level specification and partitioning in a hardware/software co-synthesis environment.
Proceedings of the Third International Workshop on Hardware/Software Codesign, 1994

1992
Compiling VHDL into a high-level synthesis design representation.
Proceedings of the conference on European design automation, 1992


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