Noppanunt Utamaphethai

According to our database, Noppanunt Utamaphethai authored at least 7 papers between 1998 and 2001.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2001

Relating buffer-oriented microarchitecture validation to high-level pipeline functionality.

Noppanunt Utamaphethai, Ronald D. Blanton, John Paul Shen

Proceedings of the Sixth IEEE International High-Level Design Validation and Test Workshop 2001, 2001

2000

A Buffer-Oriented Methodology for Microarchitecture Validation.

Noppanunt Utamaphethai, R. D. (Shawn) Blanton, John Paul Shen

J. Electron. Test., 2000

Effectiveness of Microarchitecture Test Program Generation.

Noppanunt Utamaphethai, R. D. (Shawn) Blanton, John Paul Shen

IEEE Des. Test Comput., 2000

1999

An integrated functional performance simulator.

Candice Bechem, Jonathan Combs, Noppanunt Utamaphethai, Bryan Black, R. D. (Shawn) Blanton, John Paul Shen

IEEE Micro, 1999

Superscalar Processor Validation at the Microarchitecture Level.

Noppanunt Utamaphethai, R. D. (Shawn) Blanton, John Paul Shen

Proceedings of the 12th International Conference on VLSI Design (VLSI Design 1999), 1999

1998

Dicaf: A Distributed Architecture for Intelligent Transportation.

Noppanunt Utamaphethai, Sumit Ghosh

Computer, 1998

Load Execution Latency Reduction.

Bryan Black, Brian Mueller, Stephanie Postal, Ryan N. Rakvic, Noppanunt Utamaphethai, John Paul Shen

Proceedings of the 12th international conference on Supercomputing, 1998