Ryan N. Rakvic

According to our database1, Ryan N. Rakvic authored at least 38 papers between 1998 and 2020.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

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PhD thesis 
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Bibliography

2020
Classifying Proprietary Firmware on a Solid State Drive Using Idle State Current Draw Measurements.
IEEE Access, 2020

Efficient architecture design for the AES-128 algorithm on embedded systems.
Proceedings of the 17th ACM International Conference on Computing Frontiers, 2020

2019
Monitoring Device Current to Characterize Trim Operations of Solid-State Drives.
IEEE Trans. Inf. Forensics Secur., 2019

Using Current Draw Analysis to Identify Suspicious Firmware Behavior in Solid State Drives.
Proceedings of the 2019 IEEE International Conference on Computational Science and Engineering, 2019

2018
Another dimension in integrated circuit trust.
J. Cryptogr. Eng., 2018

Towards detection of modified firmware on solid state drives via side channel analysis.
Proceedings of the International Symposium on Memory Systems, 2018

Classifying Solid State Drive Firmware via Side-Channel Current Draw Analysis.
Proceedings of the 2018 IEEE 16th Intl Conf on Dependable, 2018

2017
Face detection with a Viola-Jones based hybrid network.
IET Biom., 2017

2016
Use of synthetic data to test biometric algorithms.
J. Electronic Imaging, 2016

Energy Efficient Iris Recognition With Graphics Processing Units.
IEEE Access, 2016

Inferring read and write operations of solid-state drives based on energy consumption.
Proceedings of the 7th IEEE Annual Ubiquitous Computing, 2016

Inferring trimming activity of solid-state drives based on energy consumption.
Proceedings of the IEEE International Instrumentation and Measurement Technology Conference, 2016

2015
Iris Acquisition Device.
Proceedings of the Encyclopedia of Biometrics, Second Edition, 2015

Segmentation of Off-Axis Iris Images.
Proceedings of the Encyclopedia of Biometrics, Second Edition, 2015

Iris unwrapping using the Bresenham circle algorithm for real-time iris recognition.
Proceedings of the Real-Time Image and Video Processing 2015, 2015

2014
Resource-aware architecture design and implementation of hough transform for a real-time iris boundary detection system.
IEEE Trans. Consumer Electron., 2014

2013
Replacement techniques for dynamic NUCA cache designs on CMPs.
J. Supercomput., 2013

Real-time video surveillance on an embedded, programmable platform.
Microprocess. Microsystems, 2013

2012
Real Time Iris Segmentation on FPGA.
Proceedings of the 23rd IEEE International Conference on Application-Specific Systems, 2012

2011
Case for a field-programmable gate array multicore hybrid machine for an image-processing application.
J. Electronic Imaging, 2011

2010
Thread-management techniques to maximize efficiency in multicore and simultaneous multithreaded microprocessors.
TACO, 2010

Energy efficiency via thread fusion and value reuse.
IET Comput. Digit. Tech., 2010

Comparing an FPGA to a Cell for an Image Processing Application.
EURASIP J. Adv. Signal Process., 2010

2009
Iris Acquisition Device.
Proceedings of the Encyclopedia of Biometrics, 2009

Segmentation of Off-Axis Iris Images.
Proceedings of the Encyclopedia of Biometrics, 2009

Parallelizing iris recognition.
IEEE Trans. Inf. Forensics Secur., 2009

Iris matching with configurable hardware.
Proceedings of the Real-Time Image and Video Processing 2009, 2009

2008
Thread fusion.
Proceedings of the 2008 International Symposium on Low Power Electronics and Design, 2008

An artificial neural network based matching metric for iris identification.
Proceedings of the Image Processing: Algorithms and Systems VI, 2008

Meeting points: using thread criticality to adapt multicore hardware to parallel regions.
Proceedings of the 17th International Conference on Parallel Architectures and Compilation Techniques, 2008

2006
Multiple Instruction Stream Processor.
Proceedings of the 33rd International Symposium on Computer Architecture (ISCA 2006), 2006

A comprehensive study of hardware/software approaches to improve TLB performance for java applications on embedded systems.
Proceedings of the 2006 workshop on Memory System Performance and Correctness, 2006

2004
The Fuzzy Correlation between Code and Performance Predictability.
Proceedings of the 37th Annual International Symposium on Microarchitecture (MICRO-37 2004), 2004

2002
Compiler managed micro-cache bypassing for high performance EPIC processors.
Proceedings of the 35th Annual International Symposium on Microarchitecture, 2002

Non-Vital Loads.
Proceedings of the Eighth International Symposium on High-Performance Computer Architecture (HPCA'02), 2002

2001
Parallel Cachelets.
Proceedings of the 19th International Conference on Computer Design (ICCD 2001), 2001

2000
Completion time multiple branch prediction for enhancing trace cache performance.
Proceedings of the 27th International Symposium on Computer Architecture (ISCA 2000), 2000

1998
Load Execution Latency Reduction.
Proceedings of the 12th international conference on Supercomputing, 1998


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