Oguzhan Erdem

Orcid: 0000-0002-0020-3858

According to our database1, Oguzhan Erdem authored at least 22 papers between 2009 and 2023.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Dataset
Other 

Links

On csauthors.net:

Bibliography

2023
MSCCov19Net: multi-branch deep learning model for COVID-19 detection from cough sounds.
Medical Biol. Eng. Comput., 2023

2020
Bit vector-coded simple CART structure for low latency traffic classification on FPGAs.
Comput. Networks, 2020

2018
Musical Feature Based Classification of Parkinson's Disease Using Dysphonic Speech.
Proceedings of the 41st International Conference on Telecommunications and Signal Processing, 2018

Real-Time Traffic Classification using Simple CART Forest on FPGAs.
Proceedings of the IEEE 19th International Conference on High Performance Switching and Routing, 2018

2017
Simple CART based real-time traffic classification engine on FPGAs.
Proceedings of the International Conference on ReConFigurable Computing and FPGAs, 2017

2016
Pipelined hierarchical architecture for high performance packet classification.
Comput. Networks, 2016

Tree-based string pattern matching on FPGAs.
Comput. Electr. Eng., 2016

2015
Multi-pipelined and memory-efficient packet classification engines on FPGAs.
Comput. Commun., 2015

Value-Coded Trie Structure for High-Performance IPv6 Lookup.
Comput. J., 2015

2014
Large-scale SRAM-based IP lookup architectures using compact trie search structures.
Comput. Electr. Eng., 2014

2013
Range tree-linked list hierarchical search structure for packet classification on FPGAs.
Proceedings of the 2012 International Conference on Reconfigurable Computing and FPGAs, 2013

Clustered Linked List Forest for IPv6 Lookup.
Proceedings of the IEEE 21st Annual Symposium on High-Performance Interconnects, 2013

2012
High-performance IP Lookup Engine with Compact Clustered Trie Search.
Comput. J., 2012

Compact trie forest: Scalable architecture for IP lookup on FPGAs.
Proceedings of the 2012 International Conference on Reconfigurable Computing and FPGAs, 2012

Hierarchical hybrid search structure for high performance packet classification.
Proceedings of the IEEE INFOCOM 2012, Orlando, FL, USA, March 25-30, 2012, 2012

Scalable architecture for 135 GBPS IPv6 lookup on FPGA (abstract only).
Proceedings of the ACM/SIGDA 20th International Symposium on Field Programmable Gate Arrays, 2012

2011
Parallel and pipelined architectures for high speed ip packet forwarding ; Yüksek hızlı internet paketi (IP) yönlendirmesi için paralel ve boru hattı davranışlı mimariler.
PhD thesis, 2011

Clustered Hierarchical Search Structure for Large-Scale Packet Classification on FPGA.
Proceedings of the International Conference on Field Programmable Logic and Applications, 2011

High Performance IP Lookup on FPGA with Combined Length-Infix Pipelined Search.
Proceedings of the IEEE 19th Annual International Symposium on Field-Programmable Custom Computing Machines, 2011

Hybrid Data Structure for IP Lookup in Virtual Routers Using FPGAs.
Proceedings of the IEEE 19th Annual International Symposium on Field-Programmable Custom Computing Machines, 2011

2010
Array Design for Trie-based IP Lookup.
IEEE Commun. Lett., 2010

2009
MIPS extension for a TCAM based parallel architecture for fast IP lookup.
Proceedings of the 24th International Symposium on Computer and Information Sciences, 2009


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