Oleg Maslennikov

Orcid: 0000-0002-8909-321X

Affiliations:
  • Technical University of Koszalin, Poland


According to our database1, Oleg Maslennikov authored at least 20 papers between 1995 and 2020.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of five.

Timeline

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Bibliography

2020
Dynamics of spiking map-based neural networks in problems of supervised learning.
Commun. Nonlinear Sci. Numer. Simul., 2020

2016
Dynamic Trust Management Framework for Robotic Multi-Agent Systems.
Proceedings of the Internet of Things, Smart Spaces, and Next Generation Networks and Systems, 2016

Efficiency metrics for flocking with implicit leadership.
Proceedings of the 18th Conference of Open Innovations Association and Seminar on Information Security and Protection of Information Technology, 2016

2015
Evolving dynamical networks with transient cluster activity.
Commun. Nonlinear Sci. Numer. Simul., 2015

2009
Application Specific Processors for the Autoregressive Signal Analysis.
Proceedings of the Parallel Processing and Applied Mathematics, 2009

New conception and algorithm of allocation mapping for processor arrays implemented into multi-context FPGA devices.
Proceedings of the International Multiconference on Computer Science and Information Technology, 2009

2007
Parallel Implementation of Cholesky LLT-Algorithm in FPGA-Based Processor.
Proceedings of the Parallel Processing and Applied Mathematics, 2007

2006
Mapping DSP Algorithms into FPGA.
Proceedings of the Fifth International Conference on Parallel Computing in Electrical Engineering (PARELEC 2006), 2006

2005
FPGA Implementation of the Conjugate Gradient Method.
Proceedings of the Parallel Processing and Applied Mathematics, 2005

2003
Configurable Microprocessor Array for DSP Applications.
Proceedings of the Parallel Processing and Applied Mathematics, 2003

2002
Configurable Microcontroller Array.
Proceedings of the 2002 International Conference on Parallel Computing in Electrical Engineering (PARELEC 2002), 2002

Current-mode digital gates and circuits: concept, design and verification.
Proceedings of the 2002 9th IEEE International Conference on Electronics, 2002

2001
Implementation of Givens QR-Decomposition in FPGA.
Proceedings of the Parallel Processing and Applied Mathematics, 2001

Systematic Generation of Executing Programs for Processor Elements in Parallel ASIC or FPGA-Based Systems and Their Transformation into VHDL-Descriptions of Processor Element Control Units.
Proceedings of the Parallel Processing and Applied Mathematics, 2001

1998
Fault Tolerant QR-Decomposition Algorithm and Its Parallel Implementation.
Proceedings of the Euro-Par '98 Parallel Processing, 1998

A Method for Mapping DSP Algorithms into Application Specific Structures.
Proceedings of the 24th EUROMICRO '98 Conference, 1998

1997
A new orthogonal version of the Gauss-Jordan algorithm and its parallel implementation.
Proceedings of the Fifth Euromicro Workshop on Parallel and Distributed Processing (PDP '97), 1997

1996
Algorithm-Based Fault Tolerant Solution of Linear Systems on Processor Arrays.
Proceedings of the Parcella 1996, 1996

Processor Array for Signal Computing and Numerical Applications.
Proceedings of the Parcella 1996, 1996

1995
VLSI Implementation of Linear Algebraic Operations Based on the Orthogonal Fadddeev Algorithm.
Proceedings of the Parallel Computing: State-of-the-Art and Perspectives, 1995


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