Otmane Aït Mohamed

Orcid: 0000-0003-1378-1443

Affiliations:
  • Concordia University, Montreal, Canada


According to our database1, Otmane Aït Mohamed authored at least 126 papers between 1995 and 2023.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

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Bibliography

2023
A framework for modeling and analyzing cyber-physical systems using statistical model checking.
Internet Things, July, 2023

Toward a context-driven deployment optimization for embedded systems: a product line approach.
J. Supercomput., 2023

An Enhanced Interface-Based Probabilistic Compositional Verification Approach.
Proceedings of the Verification and Evaluation of Computer and Communication Systems, 2023

Statistical Model Checking based Analysis of Fault Trees and Power Consumption to Enhance Autonomous Systems Reliability.
Proceedings of the 21st IEEE Interregional NEWCAS Conference, 2023

Towards a Classification of Log Parsing Errors.
Proceedings of the 31st IEEE/ACM International Conference on Program Comprehension, 2023

Layout-based reliability analysis of openMSP430 register file under external radiations.
Proceedings of the International Conference on Microelectronics, 2023

2022
META: A Layout Based Tool to Estimate the Vulnerability of Digital Circuits to Multiple Event Transient.
Proceedings of the 20th IEEE Interregional NEWCAS Conference, 2022

Layout-based Vulnerability Analysis of LEON3 Processor to Single Event Multiple Transients using Satisfiability Modulo Theories.
Proceedings of the 23rd International Symposium on Quality Electronic Design, 2022

An Effective Approach for Parsing Large Log Files.
Proceedings of the IEEE International Conference on Software Maintenance and Evolution, 2022

SEU Reliability Assessment Framework for COTS Many-core Processors.
Proceedings of the International Conference on Microelectronics, 2022

2021
Towards Safe and Robust Closed-Loop Artificial Pancreas Using Improved PID-Based Control Strategies.
IEEE Trans. Circuits Syst. I Regul. Pap., 2021

Reliability-driven Automotive Software Deployment based on a Parametrizable Probabilistic Model Checking.
Expert Syst. Appl., 2021

AWSOM-LP: An Effective Log Parsing Technique Using Pattern Recognition and Frequency Analysis.
CoRR, 2021

Dynamic Fault Tree Analysis and Risk Mitigation Strategies of Data Communication System via Statistical Model Checking.
Proceedings of the 19th IEEE International New Circuits and Systems Conference, 2021

Reliability Analysis Of Autonomous UAV Communication Using Statistical Model Checking.
Proceedings of the 64th IEEE International Midwest Symposium on Circuits and Systems, 2021

2020
Routing and Scheduling of Time-Triggered Traffic in Time-Sensitive Networks.
IEEE Trans. Ind. Informatics, 2020

Towards Safe and Robust Closed-Loop Artificial Pancreas Using Adaptive Weighted PID Control Strategy.
Proceedings of the 18th IEEE International New Circuits and Systems Conference, 2020

System-Level Modeling and Safety Analysis of Vehicular Coordinated Emergency Braking Under Degraded Wireless Connectivity Using Priced Timed Automata.
Proceedings of the 27th IEEE International Conference on Electronics, Circuits and Systems, 2020

System-Level Analysis of Closed-Loop Anesthesia Control Under Temporal Sensor Faults via UPPAAL-SMC.
Proceedings of the 42nd Annual International Conference of the IEEE Engineering in Medicine & Biology Society, 2020

2019
Dependability modeling and optimization of triple modular redundancy partitioning for SRAM-based FPGAs.
Reliab. Eng. Syst. Saf., 2019

Safety analysis of train control system based on model-driven design methodology.
Comput. Ind., 2019

Towards an Accurate Probabilistic Modeling and Statistical Analysis of Temporal Faults via Temporal Dynamic Fault-Trees (TDFTs).
IEEE Access, 2019

High-Level Availability Analysis of FPGA-Based Time-Sensitive Networks.
Proceedings of the 17th IEEE International New Circuits and Systems Conference, 2019

Reliability Analysis of TSN Networks Under SEU Induced Soft Error Using Model Checking.
Proceedings of the IEEE Latin American Test Symposium, 2019

Probabilistic High-Level Estimation of Vulnerability and Fault Mitigation of Critical Systems Using Fault-Mitigation Trees (FMTs).
Proceedings of the IEEE Latin American Test Symposium, 2019

MulMapper: Towards an Automated FPGA-Based CNN Processor Generator Based on a Dynamic Design Space Exploration.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2019

Towards System Level Security Analysis of Artificial Pancreas Via UPPAAL-SMC.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2019

Multipath Routing of Mixed-Critical Traffic in Time Sensitive Networks.
Proceedings of the Advances and Trends in Artificial Intelligence. From Theory to Practice, 2019

2018
A hybrid camera- and ultrasound-based approach for needle localization and tracking using a 3D motorized curvilinear ultrasound probe.
Medical Image Anal., 2018

Formal Dependability Modeling and Optimization of Scrubbed-Partitioned TMR for SRAM-based FPGAs.
CoRR, 2018

Technological Advances in Applied Intelligence (IEA/AIE-2018).
AI Mag., 2018

New Insights Into Soft-Faults Induced Cardiac Pacemakers Malfunctions Analyzed at System-Level via Model Checking.
IEEE Access, 2018

Fault-Resilient Topology Planning and Traffic Configuration for IEEE 802.1Qbv TSN Networks.
Proceedings of the 24th IEEE International Symposium on On-Line Testing And Robust System Design, 2018

Reliability-Aware Routing of AVB Streams in TSN Networks.
Proceedings of the Recent Trends and Future Technology in Applied Intelligence, 2018

Reliability Analysis of the SPARC V8 Architecture via Fault Trees and UPPAL-SMC.
Proceedings of the 25th IEEE International Conference on Electronics, Circuits and Systems, 2018

2017
Formal analysis of SEU mitigation for early dependability and performability analysis of FPGA-based space applications.
J. Appl. Log., 2017

Formal Methods Based Synthesis of Single Event Transient Tolerant Combinational Circuits.
J. Electron. Test., 2017

Hybrid possibilistic-genetic technique for assessment of brain tissues volume: Case study for Alzheimer patients images clustering.
Proceedings of the 18th IEEE/ACIS International Conference on Software Engineering, 2017

Analysis of SEU propagation in sequential circuits at RTL using Satisfiability Modulo Theories.
Proceedings of the 15th IEEE International New Circuits and Systems Conference, 2017

Diagnosis of Auditory Pathologies with Hidden Markov Models.
Proceedings of the Bioinformatics and Biomedical Engineering, 2017

Brain tissue classification of alzheimer disease using partial volume possibilistic modeling: Application to ADNI phantom images.
Proceedings of the Seventh International Conference on Image Processing Theory, 2017

Comprehensive analysis of sequential circuits vulnerability to transient faults using SMT.
Proceedings of the 23rd IEEE International Symposium on On-Line Testing and Robust System Design, 2017

Analysis of SEU Propagation in Combinational Circuits at RTL Based on Satisfiability Modulo Theories.
Proceedings of the on Great Lakes Symposium on VLSI 2017, 2017

Fuzzy clustering optimized with genetic algorithms: Application for hybrid speech recognition system.
Proceedings of the 4th International Conference on Control, 2017

HMM/MLP speech recognition system using a novel data clustering approach.
Proceedings of the 30th IEEE Canadian Conference on Electrical and Computer Engineering, 2017

2016
Applying formal verification to early assessment of FPGA-based aerospace applications: Methodology and experience.
Proceedings of the Annual IEEE Systems Conference, 2016

Formal analysis of fault tree using probabilistic model checking: A solar array case study.
Proceedings of the Annual IEEE Systems Conference, 2016

A low-cost camera-based transducer tracking system for freehand three-dimensional ultrasound.
Proceedings of the 14th IEEE International New Circuits and Systems Conference, 2016

Towards code generation for ARM Cortex-M MCUs from SysML activity diagrams.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2016

Towards formal abstraction, modeling, and analysis of Single Event Transients at RTL.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2016

Investigating the efficiency and accuracy of a data type reduction technique for soft error analysis.
Proceedings of the 2016 IEEE International Conference on Electronics, Circuits and Systems, 2016

Efficient and accurate analysis of single event transients propagation using SMT-based techniques.
Proceedings of the 35th International Conference on Computer-Aided Design, 2016

Comprehensive non-functional analysis of combinational circuits vulnerability to single event transients.
Proceedings of the 2016 Forum on Specification and Design Languages, 2016

Efficient probabilistic fault tree analysis of safety critical systems via probabilistic model checking.
Proceedings of the 2016 Forum on Specification and Design Languages, 2016

2015
Characterizing, modeling, and analyzing soft error propagation in asynchronous and synchronous digital circuits.
Microelectron. Reliab., 2015

A quantitative verification framework of SysML activity diagrams under time constraints.
Expert Syst. Appl., 2015

Special issue on contributions of computational intelligence in designing complex information systems.
Computing, 2015

On the Probabilistic Verification of Time Constrained SysML State Machines.
Proceedings of the Intelligent Software Methodologies, Tools and Techniques, 2015

Optimum domain partitioning to increase functional verification coverage.
Proceedings of the Sixteenth International Symposium on Quality Electronic Design, 2015

Efficient multilevel formal analysis and estimation of design vulnerability to Single Event Transients.
Proceedings of the 21st IEEE International On-Line Testing Symposium, 2015

Formal modeling, verification and implementation of a train control system.
Proceedings of the 27th International Conference on Microelectronics, 2015

A methodology to generate evenly distributed input stimuli by clustering of variable domain.
Proceedings of the 33rd IEEE International Conference on Computer Design, 2015

Towards an accurate reliability, availability and maintainability analysis approach for satellite systems based on probabilistic model checking.
Proceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition, 2015

2014
A property-based abstraction framework for SysML activity diagrams.
Knowl. Based Syst., 2014

A formal verification framework for SysML activity diagrams.
Expert Syst. Appl., 2014

Modeling, analyzing, and abstracting single event transient propagation at gate level.
Proceedings of the IEEE 57th International Midwest Symposium on Circuits and Systems, 2014

Probabilistic model checking based DAL analysis to optimize a combined TMR-blind-scrubbing mitigation technique for FPGA-based aerospace applications.
Proceedings of the Twelfth ACM/IEEE International Conference on Formal Methods and Models for Codesign, 2014

Abstracting Single Event Transient characteristics variations due to input patterns and fan-out.
Proceedings of the IEEE International Symposium on Circuits and Systemss, 2014

Automatic mapping of AF3 specifications to ARM cortex-M based FRDM platfrom.
Proceedings of the 26th International Conference on Microelectronics, 2014

Probabilistic model checking of single event transient propagation at RTL level.
Proceedings of the 21st IEEE International Conference on Electronics, Circuits and Systems, 2014

2013
Automatic verification of reduction techniques in Higher Order Logic.
Formal Aspects Comput., 2013

A Security Risk Assessment Framework for SysML Activity Diagrams.
Proceedings of the IEEE 7th International Conference on Software Security and Reliability, 2013

A probabilistic verification framework of SysML activity diagrams.
Proceedings of the IEEE 12th International Conference on Intelligent Software Methodologies, 2013

Coverage Driven Test Generation and Consistency Algorithm.
Proceedings of the Declarative Programming and Knowledge Management, 2013

Early Analysis of Soft Error Effects for Aerospace Applications Using Probabilistic Model Checking.
Proceedings of the Formal Techniques for Safety-Critical Systems, 2013

A formal verification framework for Bluespec System Verilog.
Proceedings of the 2013 Forum on specification and Design Languages, 2013

Symmetry Reduction of Time-Triggered Ethernet Protocol.
Proceedings of the 4th International Conference on Ambient Systems, 2013

2012
Probabilistic Attack Scenarios to Evaluate Policies over Communication Protocols.
J. Softw., 2012

MDG-SAT: an automated methodology for efficient safety checking.
Int. J. Crit. Comput. Based Syst., 2012

Towards an FPGA implementation and performance evaluation of a digital carrier synchronizer with a portable emulation environment.
Int. J. Comput. Appl. Technol., 2012

Abstract property language for MDG model checking methodology.
Int. J. Comput. Appl. Technol., 2012

Formal proof of integer adders using all-prefix-sums operation.
Sci. China Inf. Sci., 2012

Efficient Probabilistic Abstraction for SysML Activity Diagrams.
Proceedings of the Software Engineering and Formal Methods - 10th International Conference, 2012

Probabilistic model checking of clock domain crossing interfaces.
Proceedings of the 10th IEEE International NEWCAS Conference, 2012

Performance analysis of TBCD protocol over Wireless Body channel.
Proceedings of the 55th IEEE International Midwest Symposium on Circuits and Systems, 2012

Modeling discrete event system with distributions using SystemVerilog.
Proceedings of the 2012 IEEE International Symposium on Circuits and Systems, 2012

Identification of soft error glitch-propagation paths: Leveraging SAT solvers.
Proceedings of the 2012 IEEE International Symposium on Circuits and Systems, 2012

A novel hybrid FIFO asynchronous clock domain crossing interfacing method.
Proceedings of the Great Lakes Symposium on VLSI 2012, 2012

2011
NuMDG: A New Tool for Multiway Decision Graphs Construction.
J. Comput. Sci. Technol., 2011

Model-based systems security quantification.
Proceedings of the Ninth Annual Conference on Privacy, Security and Trust, 2011

SEGP-Finder: Tool for identification of Soft Error Glitch-Propagating paths at gate level.
Proceedings of the 18th IEEE International Conference on Electronics, Circuits and Systems, 2011

Performance analysis of constraint solvers for coverage directed test generation: A car sequencing problem.
Proceedings of the 24th Canadian Conference on Electrical and Computer Engineering, 2011

2010
Field programmable gate array prototyping of end-around carry parallel prefix tree architectures.
IET Comput. Digit. Tech., 2010

Verification of the Correctness in Composed UML Behavioural Diagrams.
Proceedings of the Software Engineering Research, 2010

MDGs Reduction Technique Based on the HOL Theorem Prover.
Proceedings of the 40th IEEE International Symposium on Multiple-Valued Logic, 2010

2009
An Abstract Reachability Approach by Combining HOL Induction and Multiway Decision Graphs.
J. Comput. Sci. Technol., 2009

A case study on system-level modeling by aspect-oriented programming.
Proceedings of the 10th International Symposium on Quality of Electronic Design (ISQED 2009), 2009

TBCD-TDM: Novel Ultra-Low Energy Protocol for Implantable Wireless Body Sensor Networks.
Proceedings of the Global Communications Conference, 2009. GLOBECOM 2009, Honolulu, Hawaii, USA, 30 November, 2009

A Comparative Study of Parallel Prefix Adders in FPGA Implementation of EAC.
Proceedings of the 12th Euromicro Conference on Digital System Design, 2009

LCF-style for Secure Verification Platform based on Multiway Decision Graphs.
Proceedings of the 2nd Conférence Internationale sur l'Informatique et ses Applications (CIIA'09), 2009

2008
LCF-style Platform based on Multiway Decision Graphs.
Proceedings of the 17th International Workshop on Functional and (Constraint) Logic Programming, 2008

Reachability analysis using multiway decision graphs in the HOL theorem prover.
Proceedings of the 2008 ACM Symposium on Applied Computing (SAC), 2008

A New Approach for the Construction of Multiway Decision Graphs.
Proceedings of the Theoretical Aspects of Computing, 2008

The Performance of Combining Multiway Decision Graphs and HOL Theorem Prover.
Proceedings of the Forum on specification and Design Languages, 2008

2007
Towards First-Order Symbolic Trajectory Evaluation.
Proceedings of the 37th International Symposium on Multiple-Valued Logic, 2007

Analysis and Performance Evaluation of a Digital Carrier Synchronizer for Modem Applications.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2007), 2007

A New 10 Gbps Traffic Management algorithm for High-speed Networks.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2007), 2007

Autometic Generation of SystemC Transactors from AsmL Specification.
Proceedings of the Forum on specification and Design Languages, 2007

2006
Efficient assertion based verification using TLM.
Proceedings of the Conference on Design, Automation and Test in Europe, 2006

MDG-Based Verification of the Look-Aside Interface.
Proceedings of the Canadian Conference on Electrical and Computer Engineering, 2006

2005
FPGA implementation of a modular and pipelined WF scheduler for high speed OC192 networks.
Proceedings of the 15th ACM Great Lakes Symposium on VLSI 2005, 2005

2004
MDG-Based State Enumeration By Retiming And Circuit Transformation.
J. Circuits Syst. Comput., 2004

Model Checking for a First-Order Temporal Logic Using Multiway Decision Graphs (MDGs).
Comput. J., 2004

A scalable and pipelined FPGA implementation of an OC192 WF scheduler.
Proceedings of the 2004 IEEE International Conference on Field-Programmable Technology, 2004

An FPGA implementation of a modified version of RED algorithm.
Proceedings of the 2004 IEEE International Conference on Field-Programmable Technology, 2004

On the Design and Verification Methodology of the Look-Aside Interface.
Proceedings of the 2004 Design, 2004

First-Order LTL Model Checking Using MDGs.
Proceedings of the Automated Technology for Verification and Analysis: Second International Conference, 2004

2003
On the non-termination of M-based abstract state enumeration.
Theor. Comput. Sci., 2003

2000
Formal hardware verification by integrating HOL and MDG.
Proceedings of the 10th ACM Great Lakes Symposium on VLSI 2000, 2000

1999
Modeling and formal verification of the Fairisle ATM switch fabricusing MDGs.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1999

1998
MDG-based Verification by Retiming and Combinational Transformations.
Proceedings of the 8th Great Lakes Symposium on VLSI (GLS-VLSI '98), 1998

Model Checking for a First-Order Temporal Logic Using Multiway Decision Graphs.
Proceedings of the Computer Aided Verification, 10th International Conference, 1998

1997
On the non-termination of MDGs-based abstract state enumeration.
Proceedings of the Advances in Hardware Design and Verification, 1997

1996
La théorie du pi-calcul dans le système HOL. (The pi-calculus theory in the HOL system).
PhD thesis, 1996

1995
Mechanizing a pi-Calculus Equivalence in HOL.
Proceedings of the Higher Order Logic Theorem Proving and Its Applications, 1995

On Formal Verification of Occam Programs.
Proceedings of the International Conference on Parallel and Distributed Processing Techniques and Applications, 1995


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