Sébastien Le Beux

According to our database1, Sébastien Le Beux authored at least 59 papers between 2006 and 2020.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Other 

Links

On csauthors.net:

Bibliography

2020
3D logic cells design and results based on Vertical NWFET technology including tied compact model.
CoRR, 2020

OSCAR: An Optical Stochastic Computing AcceleRator for Polynomial Functions.
Proceedings of the 2020 Design, Automation & Test in Europe Conference & Exhibition, 2020

2019
Thermal-Aware Design Method for Laser Group Control in Nanophotonic Interconnects.
IEEE Trans. Very Large Scale Integr. Syst., 2019

A comprehensive compact model for the design of all-spin-logic based circuits.
Microelectron. J., 2019

Approximate nanophotonic interconnects.
Proceedings of the 13th IEEE/ACM International Symposium on Networks-on-Chip, 2019

Stochastic Computing with Integrated Optics.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2019

2018
Guest Editorial: Emerging Technologies and Architectures for Manycore Computing Part 1: Hardware Techniques.
IEEE Trans. Multi Scale Comput. Syst., 2018

Towards Maximum Energy Efficiency in Nanophotonic Interconnects with Thermal-Aware On-Chip Laser Tuning.
IEEE Trans. Emerg. Top. Comput., 2018

Offline Optimization of Wavelength Allocation and Laser Power in Nanophotonic Interconnects.
ACM J. Emerg. Technol. Comput. Syst., 2018

Run-Time management of energy-performance trade-off in Optical Network-on-Chip.
Proceedings of the Conference on Design of Circuits and Integrated Systems, 2018

Large scale, high density integration of all spin logic.
Proceedings of the 2018 Design, Automation & Test in Europe Conference & Exhibition, 2018

2017
Energy-Efficiency Comparison of Multi-Layer Deposited Nanophotonic Crossbar Interconnects.
ACM J. Emerg. Technol. Comput. Syst., 2017

Arithmetic Logic Unit based on all-spin logic devices.
Proceedings of the 15th IEEE International New Circuits and Systems Conference, 2017

An Energy-Efficient Reconfigurable Nanophotonic Computing Architecture Design: Optical Lookup Table.
Proceedings of the IEEE International Conference on Rebooting Computing, 2017

Hybrid Topologies for Reconfigurable Matrices Based on Nano-Grain Cells.
Proceedings of the IEEE International Conference on Rebooting Computing, 2017

Performance and energy aware wavelength allocation on ring-based WDM 3D optical NoC.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2017

Energy and Performance Trade-off in Nanophotonic Interconnects using Coding Techniques.
Proceedings of the 54th Annual Design Automation Conference, 2017

2016
Coherent and Incoherent Crosstalk Noise Analyses in Interchip/Intrachip Optical Interconnection Networks.
IEEE Trans. Very Large Scale Integr. Syst., 2016

2015
Multi-Level Mapping of Nanocomputer Architectures Based on Hardware Reuse.
IEEE J. Emerg. Sel. Topics Circuits Syst., 2015

Full-adder circuit design based on all-spin logic device.
Proceedings of the 2015 IEEE/ACM International Symposium on Nanoscale Architectures, 2015

Communication Aware Design Method for Optical Network-on-Chip.
Proceedings of the IEEE 9th International Symposium on Embedded Multicore/Many-core Systems-on-Chip, 2015

Multilevel Modeling Methodology for Reconfigurable Computing Systems Based on Silicon Photonics.
Proceedings of the 2015 IEEE Computer Society Annual Symposium on VLSI, 2015

Channel Allocation Protocol for Reconfigurable Optical Network-on-Chip.
Proceedings of the 2015 Workshop on Exploiting Silicon Photonics for Energy-Efficient High Performance Computing, 2015

Thermal aware design method for VCSEL-based on-chip optical interconnect.
Proceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition, 2015

Coherent crosstalk noise analyses in ring-based optical interconnects.
Proceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition, 2015

Complementary communication path for energy efficient on-chip optical interconnects.
Proceedings of the 52nd Annual Design Automation Conference, 2015

Energy-efficient optical crossbars on chip with multi-layer deposited silicon.
Proceedings of the 20th Asia and South Pacific Design Automation Conference, 2015

2014
A Case Study of Signal-to-Noise Ratio in Ring-Based Optical Networks-on-Chip.
IEEE Des. Test, 2014

Optical crossbars on chip, a comparative study based on worst-case losses.
Concurr. Comput. Pract. Exp., 2014

Complementary logic interface for high performan optical computing with OLUT.
Proceedings of the 22nd International Conference on Very Large Scale Integration, 2014

A reconfigurable optical network on chip for streaming applications.
Proceedings of the 9th International Symposium on Reconfigurable and Communication-Centric Systems-on-Chip, 2014

Introduction to the special session on "Silicon photonic interconnects: an illusion or a realistic solution?".
Proceedings of the Eighth IEEE/ACM International Symposium on Networks-on-Chip, 2014

CLAP: a crosstalk and loss analysis platform for optical interconnects.
Proceedings of the Eighth IEEE/ACM International Symposium on Networks-on-Chip, 2014

Chameleon: Channel efficient Optical Network-on-Chip.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2014

2013
Reduction methods for adapting optical network on chip topologies to 3D architectures.
Microprocess. Microsystems, 2013

Reconfigurable photonic switching: Towards all-optical FPGAs.
Proceedings of the 21st IEEE/IFIP International Conference on VLSI and System-on-Chip, 2013

Potential and pitfalls of silicon photonics computing and interconnect.
Proceedings of the 2013 IEEE International Symposium on Circuits and Systems (ISCAS2013), 2013

Optical look up table.
Proceedings of the Design, Automation and Test in Europe, 2013

2012
Ambipolar independent double gate FET logic.
Proceedings of the 2012 IEEE/ACM International Symposium on Nanoscale Architectures, 2012

Low-power design technique with ambipolar double gate devices.
Proceedings of the 2012 IEEE/ACM International Symposium on Nanoscale Architectures, 2012

Ambipolar double gate CNTFETs based reconfigurable logic cells.
Proceedings of the 2012 IEEE/ACM International Symposium on Nanoscale Architectures, 2012

Ambipolar double-gate FETs for the design of compact logic structures.
Proceedings of the Great Lakes Symposium on VLSI 2012, 2012

2011
A Model-Driven Design Framework for Massively Parallel Embedded Systems.
ACM Trans. Embed. Comput. Syst., 2011

Layout guidelines for 3D architectures including Optical Ring Network-on-Chip (ORNoC).
Proceedings of the IEEE/IFIP 19th International Conference on VLSI and System-on-Chip, 2011

Multi-objective mapping for matrix-based nanocomputer architectures.
Proceedings of the 6th International Workshop on Reconfigurable Communication-centric Systems-on-Chip, 2011

Using Self-Reconfiguration to Increase Manufacturing Yield of CNTFET-based Architectures.
Proceedings of the 2011 International Conference on Reconfigurable Computing and FPGAs, 2011

Ambipolar double-gate FET binary-decision- diagram (Am-BDD) for reconfigurable logic cells.
Proceedings of the 2011 IEEE/ACM International Symposium on Nanoscale Architectures, 2011

High performance 4: 1 multiplexer with ambipolar double-gate FETs.
Proceedings of the 18th IEEE International Conference on Electronics, Circuits and Systems, 2011

Fine-grain reconfigurable logic cells based on double-gate CNTFETs.
Proceedings of the 21st ACM Great Lakes Symposium on VLSI 2010, 2011

Optical Ring Network-on-Chip (ORNoC): Architecture and design methodology.
Proceedings of the Design, Automation and Test in Europe, 2011

2010
Combining mapping and partitioning exploration for NoC-based embedded systems.
J. Syst. Archit., 2010

Multi-Optical Network-on-Chip for Large Scale MPSoC.
IEEE Embed. Syst. Lett., 2010

A system-level exploration flow for optica network on chip (ONoC) in 3D MPSoC.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2010), May 30, 2010

2009
Optimizing Configuration and Application Mapping for MPSoC Architectures.
Proceedings of the NASA/ESA Conference on Adaptive Hardware and Systems, 2009

2007
Un flot de conception pour applications de traitement du signal systématique implémentées sur FPGA à base d'Ingénierie Dirigée par les Modèles. (A Model Driven Engineering based design flow for systematic signal processing applications implemented on FPGA).
PhD thesis, 2007

Multiple Abstraction Views of FPGA to Map Parallel Applications.
Proceedings of the 3rd International Workshop on Reconfigurable Communication-centric Systems-on-Chip, 2007

A Design Flow to Map Parallel Applications onto FPGAs.
Proceedings of the FPL 2007, 2007

Massively parallel processing on a chip.
Proceedings of the 4th Conference on Computing Frontiers, 2007

2006
FPGA Implementation of Embedded Cruise Control and Anti-Collision Radar.
Proceedings of the Ninth Euromicro Conference on Digital System Design: Architectures, Methods and Tools (DSD 2006), 30 August, 2006


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