Padmaraj Singh

According to our database, Padmaraj Singh authored at least 6 papers between 1990 and 2012.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2012

Targeted random test generation for power-aware multicore designs.

Padmaraj Singh, Vijaykrishnan Narayanan, David L. Landis

ACM Trans. Design Autom. Electr. Syst., 2012

Hazard driven test generation for SMT processors.

Padmaraj Singh, Vijaykrishnan Narayanan, David L. Landis

Proceedings of the 2012 Design, Automation & Test in Europe Conference & Exhibition, 2012

2010

Test Generation for CMP Designs.

Padmaraj Singh, David L. Landis

Proceedings of the 11th International Workshop on Microprocessor Test and Verification, 2010

2009

Test Generation for Precise Interrupts on Out-of-Order Microprocessors.

Padmaraj Singh, David L. Landis, Vijaykrishnan Narayanan

Proceedings of the 10th International Workshop on Microprocessor Test and Verification, 2009

2007

First Silicon Functional Validation and Debug of Multicore Microprocessors.

Todd J. Foster, Dennis L. Lastor, Padmaraj Singh

IEEE Trans. Very Large Scale Integr. Syst., 2007

1990

Optimal placement of IEEE 1149.1 test port and boundary scan resources for wafer scale integration.

David L. Landis, Padmaraj Singh

Proceedings of the Proceedings IEEE International Test Conference 1990, 1990